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85 lines
1.8 KiB
Verilog
85 lines
1.8 KiB
Verilog
module uart_top(
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input wire sys_clk ,
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input wire sys_rst_n ,
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input wire rx ,
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output wire tx ,
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output wire led_ready
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);
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wire [7: 0] data_byte ;
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wire [7: 0] data_out ;
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wire ready ;
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wire comm_finish ;
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wire tx_vld ;
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wire rx_vld ;
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reg rcv_start ;
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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rcv_start <= 1'b1;
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end
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else if(ready)begin
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rcv_start <= 1'b0;
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end
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else if(comm_finish)begin
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rcv_start <= 1'b1;
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end
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else begin
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rcv_start <= rcv_start;
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end
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end
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uart_rx uart_rx_inst(
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.sys_clk (sys_clk) ,
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.sys_rst_n (sys_rst_n) ,
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.rx_din (rx) ,//数据串行输入
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.rcv_start (rcv_start) ,
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.rx_dout (data_byte) ,//数据并行输出
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.rx_vld (rx_vld) //输出信号有效
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);
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uart_tx uart_tx_inst(
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.sys_clk (sys_clk) ,
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.sys_rst_n (sys_rst_n) ,
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.tx_din (data_out) ,//并行输入，接受模块传入
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.rx_vld (rx_vld) ,//接受模块，串转并有效信
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.tx_vld (tx_vld) ,
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.tx_dout (tx)//串行输出
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);
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device_ready device_ready_inst(
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.sys_clk (sys_clk) ,
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.sys_rst_n (sys_rst_n) ,
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.data_in (data_byte) ,
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.rx_vld (rx_vld) ,
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.ready (ready)
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);
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command_send command_send_inst(
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.sys_clk (sys_clk) ,
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.sys_rst_n (sys_rst_n) ,
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.tx_vld (tx_vld) ,
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.comm_finish (comm_finish),
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.data_out (data_out)
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);
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led_driver led_driver_inst(
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.sys_clk (sys_clk),
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.sys_rst_n (sys_rst_n),
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.rx_data (data_byte),
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.led_ready (led_ready)
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);
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endmodule |