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104 lines
2.5 KiB
Verilog
104 lines
2.5 KiB
Verilog
`include "param.v"
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module uart_tx(
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input wire sys_clk ,
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input wire sys_rst_n ,
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input wire [7: 0] tx_din ,//并行输入，接受模块传入
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input wire rx_vld ,//接受模块，串转并有效信号
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output wire tx_vld ,
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output reg tx_dout //串行输出
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);
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parameter BAUD = `SYS_FRQ / `MAX;//波特率最大数
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reg [8: 0] data_reg;//寄存数据，包含起始位
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reg tx_flag ;//发送数据有效信号
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//波特率计数寄存器
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reg [12: 0] cnt_bps;
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wire add_cnt_bps;
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wire end_cnt_bps;
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//比特计数寄存器
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reg [3: 0] cnt_bit;
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wire add_cnt_bit;
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wire end_cnt_bit;
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//寄存数据
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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data_reg <= 9'hx;
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end
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else if(rx_vld)begin
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data_reg <= {tx_din, 1'b0};//封装成数据帧
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end
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else begin
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data_reg <= data_reg;
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end
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end
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//tx_flag信号约束
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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tx_flag <= 1'b0;
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end
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else if(rx_vld)begin
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tx_flag <= 1'b1;
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end
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else if(end_cnt_bit)begin
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tx_flag <= 1'b0;
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end
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else begin
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tx_flag <= tx_flag;
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end
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end
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//cnt_bps计数器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_bps <= 13'd0;
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end
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else if(add_cnt_bps)begin
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if(end_cnt_bps)begin
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cnt_bps <= 13'd0;
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end
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else begin
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cnt_bps <= cnt_bps + 1'd1;
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end
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end
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else begin
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cnt_bps <= cnt_bps;
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end
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end
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assign add_cnt_bps = tx_flag;
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assign end_cnt_bps = add_cnt_bps && cnt_bps == BAUD - 1'd1;
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//cnt_bit计数器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_bit <= 4'd0;
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end
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else if(add_cnt_bit)begin
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if(end_cnt_bit)begin
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cnt_bit <= 4'd0;
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end
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else begin
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cnt_bit <= cnt_bit + 1'd1;
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end
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end
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else begin
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cnt_bit <= cnt_bit;
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end
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end
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assign add_cnt_bit = end_cnt_bps;//波特计数器结束开启
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assign end_cnt_bit = add_cnt_bit && cnt_bit == 4'd8;
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//tx_dout信号进行约束
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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tx_dout <= 1'b1;
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end
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else if(tx_flag)begin
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tx_dout <= data_reg[cnt_bit];//发送数据，并转串
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end
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else begin
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tx_dout <= 1'b1;
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end
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end
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assign tx_vld = end_cnt_bit;
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endmodule |