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module i2c_ctrl(
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input wire sys_clk ,
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input wire sys_rst_n ,
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input wire i2c_start ,
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input wire [5: 0] cfg_num ,
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input wire [15: 0] cfg_data ,
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output reg cfg_start ,
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output reg [2: 0] step ,
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output reg i2c_clk ,
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output wire scl ,
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inout wire sda ,
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output reg [7: 0] po_data
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);
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parameter I2C_CLK_DIV = 5'd24,
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MAX = 10'd1000,
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SLAVE_ID = 7'h73;
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//状态机参数定义
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parameter IDLE = 4'd0,
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START = 4'd1,
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SLAVE_ADDR = 4'd2,
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ACK_1 = 4'd3,
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ACK_2 = 4'd4,
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ACK_3 = 4'd5,
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DEVICE_ADDR = 4'd6,
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DATA = 4'd7,
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WAIT = 4'd8,
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NACK = 4'd9,
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STOP = 4'd10;
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reg [3: 0] state_c;
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reg [3: 0] state_n;
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////
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//i2c时钟计数器
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reg [4: 0] cnt_clk;
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/////
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//中间信号定义
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reg [9: 0] cnt_wait ;//1000us
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reg skip_en_1 ;//步骤1跳转信号,唤醒
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reg skip_en_2 ;//步骤2跳转信号,激活bank0
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reg skip_en_3 ;//步骤3跳转信号,配置0x00
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reg skip_en_4 ;//步骤4跳转信号,读取0x20
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reg skip_en_5 ;//步骤5跳转信号,配置51寄存器
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reg skip_en_6 ;//步骤6跳转信号,配置0x43
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reg skip_en_7 ;//步骤7跳转信号,读取0x43
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reg [1: 0] cnt_i2c_clk ;//i2c计数器
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reg [2: 0] cnt_bit ;//bit计数器
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reg i2c_end ;//i2c结束信号
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wire sda_en ;
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wire sda_in ;
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reg i2c_sda ;
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reg i2c_scl ;
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reg [7: 0] slave_addr ;
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reg [7: 0] device_addr ;
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reg [7: 0] wr_data ;
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reg [7: 0] recv_data ;//接受0x20寄存器
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reg ack ;//接受信号
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reg err_en ;//接受到0x20有误
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//三态门
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assign sda_en = ((state_c == ACK_1) || (state_c == ACK_2) || (state_c == ACK_3) || (state_c == DATA && (step == 3'd3 || step == 3'd6))) ? 1'b0: 1'b1;//发送主机控制从机，接受主机释放
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assign sda_in = sda;
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assign sda = (sda_en == 1'b1)? i2c_sda : 1'bz;
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//cfg_start
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always @(posedge i2c_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cfg_start <= 1'b0;
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end
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else begin
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cfg_start <= i2c_end;//延迟一个时钟输出
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end
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end
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//i2c驱动时钟设计
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always @(posedge sys_clk or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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cnt_clk <= 5'd0;
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end
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else if(cnt_clk == I2C_CLK_DIV)begin
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cnt_clk <= 5'd0;
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end
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else begin
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cnt_clk <= cnt_clk + 1;
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end
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end
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always @(posedge sys_clk or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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i2c_clk <= 1'b1;
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end
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else if(cnt_clk == I2C_CLK_DIV)begin
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i2c_clk <= ~i2c_clk;
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end
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else begin
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i2c_clk <= i2c_clk;
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end
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end
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/////////
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//状态机，第一段
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always @(posedge i2c_clk or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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state_c <= IDLE;
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end
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else begin
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state_c <= state_n;
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end
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end
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//状态机第二段
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always @(*)begin
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case(state_c)
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IDLE: if((skip_en_1 == 1'b1) || (skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_4 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1) || (skip_en_7 == 1'b1))begin
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state_n = START;
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end
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else begin
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state_n = IDLE;
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end
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START: if((skip_en_1 == 1'b1) || (skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_4 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1) || (skip_en_7 == 1'b1))begin
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state_n = SLAVE_ADDR;
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end
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else begin
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state_n = START;
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end
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SLAVE_ADDR: if(skip_en_1 == 1'b1)begin
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state_n = WAIT;
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end
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else if((skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_4 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1) || (skip_en_7 == 1'b1))begin
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state_n = ACK_1;
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end
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else begin
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state_n = SLAVE_ADDR;
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end
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ACK_1: if((skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1))begin
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state_n = DEVICE_ADDR;
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end
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else if((skip_en_4 == 1'b1) || (skip_en_7 == 1'b1))begin
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state_n = DATA;
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end
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else begin
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state_n = ACK_1;
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end
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DEVICE_ADDR:if((skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1))begin
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state_n = ACK_2;
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end
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else begin
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state_n = DEVICE_ADDR;
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end
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ACK_2: if((skip_en_2 == 1'b1) || (skip_en_5 == 1'b1))begin
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state_n = DATA;
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end
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else if((skip_en_3 == 1'b1) || (skip_en_6 == 1'b1))begin
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state_n = STOP;
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end
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else begin
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state_n = ACK_2;
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end
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DATA: if((skip_en_2 == 1'b1) || (skip_en_5 == 1'b1))begin
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state_n = ACK_3;
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end
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else if((skip_en_4 == 1'b1) || (skip_en_7 == 1'b1))begin
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state_n = NACK;
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end
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else if(err_en == 1'b1)begin
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state_n = IDLE;
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end
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else begin
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state_n = DATA;
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end
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NACK: if((skip_en_4 == 1'b1) || (skip_en_7 == 1'b1))begin
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state_n = STOP;
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end
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else begin
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state_n = NACK;
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end
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ACK_3: if((skip_en_2 == 1'b1) || (skip_en_5 == 1'b1))begin
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state_n = STOP;
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end
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else begin
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state_n = ACK_3;
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end
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WAIT: if(skip_en_1 == 1'b1)begin
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state_n = STOP;
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end
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else begin
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state_n = WAIT;
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end
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STOP: if((skip_en_1 == 1'b1) || (skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_4 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1) || (skip_en_7 == 1'b1))begin
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state_n = IDLE;
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end
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else begin
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state_n = STOP;
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end
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default: begin
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state_n = IDLE;
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end
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endcase
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end
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//状态机第三段
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always @(posedge i2c_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_wait <= 10'd0;
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skip_en_1 <= 1'b0;//步骤1跳转信号
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skip_en_2 <= 1'b0;//步骤2跳转信号
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skip_en_3 <= 1'b0;//步骤3跳转信号
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skip_en_4 <= 1'b0;//步骤4跳转信号
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skip_en_5 <= 1'b0;//步骤5跳转信号
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skip_en_6 <= 1'b0;//步骤6跳转信号
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skip_en_7 <= 1'b0;//步骤7跳转信号
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step <= 3'd0;
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err_en <= 1'b0;
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cnt_i2c_clk <= 2'd0;
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cnt_bit <= 3'd0;
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i2c_end <= 1'b0;
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end
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else begin
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case(state_c)
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IDLE: begin
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if(cnt_wait == MAX - 1)begin
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cnt_wait <= 10'd0;
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end
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else begin
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cnt_wait <= cnt_wait + 1;
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end
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if((cnt_wait == MAX - 2'd2) && (step == 3'd0))begin
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skip_en_1 <= 1'b1;
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end
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else begin
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skip_en_1 <= 1'b0;
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end
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if((cnt_wait == MAX - 2'd2) && (step == 3'd1))begin
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skip_en_2 <= 1'b1;
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end
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else begin
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skip_en_2 <= 1'b0;
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end
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if((cnt_wait == MAX - 2'd2) && (step == 3'd2))begin
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skip_en_3 <= 1'b1;
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end
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else begin
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skip_en_3 <= 1'b0;
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end
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if((cnt_wait == MAX - 2'd2) && (step == 3'd3))begin
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skip_en_4 <= 1'b1;
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end
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else begin
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skip_en_4 <= 1'b0;
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end
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if((cnt_wait == MAX - 2'd2) && (step == 3'd4))begin
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skip_en_5 <= 1'b1;
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end
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else begin
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skip_en_5 <= 1'b0;
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end
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if((cnt_wait == MAX - 2'd2) && (step == 3'd5))begin
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skip_en_6 <= 1'b1;
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end
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else begin
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skip_en_6 <= 1'b0;
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end
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if((cnt_wait == MAX - 2'd2) && (step == 3'd6))begin
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skip_en_7 <= 1'b1;
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end
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else begin
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skip_en_7 <= 1'b0;
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end
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end
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START: begin
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cnt_i2c_clk <= cnt_i2c_clk + 1'd1;
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if((cnt_i2c_clk == 2'd2) && (step == 3'd0))begin
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skip_en_1 <= 1'b1;
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end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_1 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd1))begin
|
|
|
|
|
|
skip_en_2 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_2 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd2))begin
|
|
|
|
|
|
skip_en_3 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_3 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd3))begin
|
|
|
|
|
|
skip_en_4 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_4 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd4))begin
|
|
|
|
|
|
skip_en_5 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_5 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd5))begin
|
|
|
|
|
|
skip_en_6 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_6 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd6))begin
|
|
|
|
|
|
skip_en_7 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_7 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
end
|
|
|
|
|
|
SLAVE_ADDR: begin
|
|
|
|
|
|
cnt_i2c_clk <= cnt_i2c_clk + 1'd1;
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd0) && (cnt_bit == 3'd7))begin
|
|
|
|
|
|
skip_en_1 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_1 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd1) && (cnt_bit == 3'd7))begin
|
|
|
|
|
|
skip_en_2 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_2 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd2) && (cnt_bit == 3'd7))begin
|
|
|
|
|
|
skip_en_3 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_3 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd3) && (cnt_bit == 3'd7))begin
|
|
|
|
|
|
skip_en_4 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_4 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd4) && (cnt_bit == 3'd7))begin
|
|
|
|
|
|
skip_en_5 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_5 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd5) && (cnt_bit == 3'd7))begin
|
|
|
|
|
|
skip_en_6 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_6 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd6) && (cnt_bit == 3'd7))begin
|
|
|
|
|
|
skip_en_7 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_7 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_bit == 3'd7) && (cnt_i2c_clk == 2'd3))begin
|
|
|
|
|
|
cnt_bit <= 3'd0;
|
|
|
|
|
|
end
|
|
|
|
|
|
else if(cnt_i2c_clk == 2'd3)begin
|
|
|
|
|
|
cnt_bit <= cnt_bit + 1'd1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
cnt_bit <= cnt_bit;
|
|
|
|
|
|
end
|
|
|
|
|
|
end
|
|
|
|
|
|
ACK_1: begin
|
|
|
|
|
|
cnt_i2c_clk <= cnt_i2c_clk + 1'd1;
|
|
|
|
|
|
if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd1))begin
|
|
|
|
|
|
skip_en_2 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_2 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd2))begin
|
|
|
|
|
|
skip_en_3 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_3 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd3))begin
|
|
|
|
|
|
skip_en_4 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_4 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd4))begin
|
|
|
|
|
|
skip_en_5 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_5 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd5))begin
|
|
|
|
|
|
skip_en_6 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_6 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd6))begin
|
|
|
|
|
|
skip_en_7 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_7 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
end
|
|
|
|
|
|
DEVICE_ADDR:begin
|
|
|
|
|
|
cnt_i2c_clk <= cnt_i2c_clk + 1'b1;
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd3) && (cnt_bit == 3'd7))begin
|
|
|
|
|
|
cnt_bit <= 3'd0;
|
|
|
|
|
|
end
|
|
|
|
|
|
else if(cnt_i2c_clk == 2'd3)begin
|
|
|
|
|
|
cnt_bit <= cnt_bit + 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
cnt_bit <= cnt_bit;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd1))begin
|
|
|
|
|
|
skip_en_2 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_2 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd2))begin
|
|
|
|
|
|
skip_en_3 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_3 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd4))begin
|
|
|
|
|
|
skip_en_5 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_5 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd5))begin
|
|
|
|
|
|
skip_en_6 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_6 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
end
|
|
|
|
|
|
ACK_2: begin
|
|
|
|
|
|
cnt_i2c_clk <= cnt_i2c_clk + 1;
|
|
|
|
|
|
if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd1))begin
|
|
|
|
|
|
skip_en_2 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_2 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd2))begin
|
|
|
|
|
|
skip_en_3 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_3 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd4))begin
|
|
|
|
|
|
skip_en_5 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_5 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd5))begin
|
|
|
|
|
|
skip_en_6 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_6 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
end
|
|
|
|
|
|
DATA: begin
|
|
|
|
|
|
cnt_i2c_clk <= cnt_i2c_clk + 1'b1;
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd3) && (cnt_bit == 3'd7))begin
|
|
|
|
|
|
cnt_bit <= 3'd0;
|
|
|
|
|
|
end
|
|
|
|
|
|
else if(cnt_i2c_clk == 2'd3)begin
|
|
|
|
|
|
cnt_bit <= cnt_bit + 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
cnt_bit <= cnt_bit;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd1))begin
|
|
|
|
|
|
skip_en_2 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_2 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd3) && (recv_data == 8'h20))begin
|
|
|
|
|
|
skip_en_4 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_4 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd4))begin
|
|
|
|
|
|
skip_en_5 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_5 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd6))begin
|
|
|
|
|
|
skip_en_7 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_7 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd3) && (recv_data != 8'h20))begin
|
|
|
|
|
|
begin
|
|
|
|
|
|
err_en <= 1'b1;
|
|
|
|
|
|
step <= 3'd0;
|
|
|
|
|
|
end
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
begin
|
|
|
|
|
|
err_en <= 1'b0;
|
|
|
|
|
|
step <= step;
|
|
|
|
|
|
end
|
|
|
|
|
|
end
|
|
|
|
|
|
end
|
|
|
|
|
|
NACK: begin
|
|
|
|
|
|
cnt_i2c_clk <= cnt_i2c_clk + 1;
|
|
|
|
|
|
if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd3))begin
|
|
|
|
|
|
skip_en_4 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_4 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd6))begin
|
|
|
|
|
|
skip_en_7 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_7 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
end
|
|
|
|
|
|
ACK_3: begin
|
|
|
|
|
|
cnt_i2c_clk <= cnt_i2c_clk + 1;
|
|
|
|
|
|
if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd1))begin
|
|
|
|
|
|
skip_en_2 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_2 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd4))begin
|
|
|
|
|
|
skip_en_5 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_5 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
end
|
|
|
|
|
|
WAIT: begin
|
|
|
|
|
|
if(cnt_wait == MAX - 1'd1)begin
|
|
|
|
|
|
cnt_wait <= 10'd0;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
cnt_wait <= cnt_wait + 1'd1;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_wait == MAX - 2'd2) && (step == 3'd0))begin
|
|
|
|
|
|
skip_en_1 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_1 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
end
|
|
|
|
|
|
STOP: begin
|
|
|
|
|
|
cnt_i2c_clk <= cnt_i2c_clk + 1'd1;
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd0))begin
|
|
|
|
|
|
skip_en_1 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_1 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd1))begin
|
|
|
|
|
|
skip_en_2 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_2 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd2))begin
|
|
|
|
|
|
skip_en_3 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_3 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd3))begin
|
|
|
|
|
|
skip_en_4 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_4 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd4))begin
|
|
|
|
|
|
skip_en_5 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_5 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd5))begin
|
|
|
|
|
|
skip_en_6 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_6 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd2) && (step == 3'd6))begin
|
|
|
|
|
|
skip_en_7 <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
skip_en_7 <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if(cnt_i2c_clk == 2'd2)begin
|
|
|
|
|
|
i2c_end <= 1'b1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
i2c_end <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
if((i2c_end == 1'b1) && ((step <= 3'd3) || step == 3'd5))begin
|
|
|
|
|
|
step <= step + 1'd1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else if((i2c_end == 1'b1) && (step == 3'd4) && (cfg_num == 6'd51))begin
|
|
|
|
|
|
step <= step + 1'd1;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
step <= step;
|
|
|
|
|
|
end
|
|
|
|
|
|
end
|
|
|
|
|
|
default: begin
|
|
|
|
|
|
cnt_wait <= 10'd0;
|
|
|
|
|
|
skip_en_1 <= 1'b0;
|
|
|
|
|
|
skip_en_2 <= 1'b0;
|
|
|
|
|
|
skip_en_3 <= 1'b0;
|
|
|
|
|
|
skip_en_4 <= 1'b0;
|
|
|
|
|
|
skip_en_5 <= 1'b0;
|
|
|
|
|
|
skip_en_6 <= 1'b0;
|
|
|
|
|
|
skip_en_7 <= 1'b0;
|
|
|
|
|
|
err_en <= 1'b0;
|
|
|
|
|
|
step <= step;
|
|
|
|
|
|
cnt_i2c_clk <= 2'd0;
|
|
|
|
|
|
cnt_bit <= 3'd0;
|
|
|
|
|
|
i2c_end <= 1'b0;
|
|
|
|
|
|
end
|
|
|
|
|
|
endcase
|
|
|
|
|
|
end
|
|
|
|
|
|
end
|
|
|
|
|
|
//recv_data
|
|
|
|
|
|
always @(posedge i2c_clk or negedge sys_rst_n)begin
|
|
|
|
|
|
if(!sys_rst_n)begin
|
|
|
|
|
|
recv_data <= 8'h0;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
case(state_c)
|
|
|
|
|
|
DATA: begin
|
|
|
|
|
|
if((cnt_i2c_clk == 2'd1) && ((step == 3'd3) || (step == 3'd6)))begin
|
|
|
|
|
|
recv_data <= {recv_data[6:0], sda_in};
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
recv_data <= recv_data;
|
|
|
|
|
|
end
|
|
|
|
|
|
end
|
|
|
|
|
|
default: recv_data <= recv_data;
|
|
|
|
|
|
endcase
|
|
|
|
|
|
end
|
|
|
|
|
|
end
|
|
|
|
|
|
//ack
|
|
|
|
|
|
always @(*)begin
|
|
|
|
|
|
case(state_c)
|
|
|
|
|
|
ACK_1, ACK_2, ACK_3: ack = ~sda_in;
|
|
|
|
|
|
NACK: ack = i2c_sda;//主机发送NACK
|
|
|
|
|
|
default: ack = 1'b0;
|
|
|
|
|
|
endcase
|
|
|
|
|
|
end
|
|
|
|
|
|
//step
|
|
|
|
|
|
always @(*)begin
|
|
|
|
|
|
case(step)
|
|
|
|
|
|
3'd0: begin
|
|
|
|
|
|
slave_addr = {SLAVE_ID, 1'b0};
|
|
|
|
|
|
device_addr = 8'h0;
|
|
|
|
|
|
wr_data = 8'h0;
|
|
|
|
|
|
end
|
|
|
|
|
|
3'd1: begin
|
|
|
|
|
|
slave_addr = {SLAVE_ID, 1'b0};
|
|
|
|
|
|
device_addr= {8'hef};
|
|
|
|
|
|
wr_data = {8'h00};
|
|
|
|
|
|
end
|
|
|
|
|
|
3'd2: begin
|
|
|
|
|
|
slave_addr = {SLAVE_ID, 1'b0};
|
|
|
|
|
|
device_addr= {8'h00};
|
|
|
|
|
|
wr_data = {8'h00};
|
|
|
|
|
|
end
|
|
|
|
|
|
3'd3: begin
|
|
|
|
|
|
slave_addr = {SLAVE_ID, 1'b1};//读取
|
|
|
|
|
|
device_addr= {8'h00};
|
|
|
|
|
|
wr_data = {8'h00};
|
|
|
|
|
|
end
|
|
|
|
|
|
3'd4: begin
|
|
|
|
|
|
slave_addr = {SLAVE_ID, 1'b0};
|
|
|
|
|
|
device_addr= cfg_data[15: 8];
|
|
|
|
|
|
wr_data = cfg_data[7: 0];
|
|
|
|
|
|
end
|
|
|
|
|
|
3'd5: begin
|
|
|
|
|
|
slave_addr = {SLAVE_ID, 1'b0};//配置
|
|
|
|
|
|
device_addr= 8'h43;
|
|
|
|
|
|
wr_data = 8'h00;
|
|
|
|
|
|
end
|
|
|
|
|
|
3'd6: begin
|
|
|
|
|
|
slave_addr = {SLAVE_ID, 1'b1};//读取
|
|
|
|
|
|
device_addr= 8'h43;
|
|
|
|
|
|
wr_data = 8'h00;
|
|
|
|
|
|
end
|
|
|
|
|
|
default:begin
|
|
|
|
|
|
slave_addr = 8'h0;
|
|
|
|
|
|
device_addr = 8'h0;
|
|
|
|
|
|
wr_data = 8'h0;
|
|
|
|
|
|
end
|
|
|
|
|
|
endcase
|
|
|
|
|
|
end
|
|
|
|
|
|
//i2c_scl
|
|
|
|
|
|
always @(*)begin
|
|
|
|
|
|
case(state_c)
|
|
|
|
|
|
IDLE: i2c_scl = 1'b1;
|
|
|
|
|
|
START: i2c_scl = (cnt_i2c_clk <= 2'd2) ? 1'b1 : 1'b0;
|
|
|
|
|
|
SLAVE_ADDR, DEVICE_ADDR, DATA, ACK_1, ACK_2, ACK_3, NACK:
|
|
|
|
|
|
i2c_scl = ((cnt_i2c_clk == 2'd1) || (cnt_i2c_clk == 2'd2)) ? 1'b1 : 1'b0;
|
|
|
|
|
|
WAIT: i2c_scl = 1'b0;
|
|
|
|
|
|
STOP: i2c_scl = (cnt_i2c_clk >= 2'd1) ? 1'b1 : 1'b0;
|
|
|
|
|
|
endcase
|
|
|
|
|
|
end
|
|
|
|
|
|
//i2c_sda
|
|
|
|
|
|
always @(*)begin
|
|
|
|
|
|
case(state_c)
|
|
|
|
|
|
IDLE: i2c_sda = 1'b1;
|
|
|
|
|
|
START: i2c_sda = (cnt_i2c_clk > 2'd1) ? 1'b0 : 1'b1;
|
|
|
|
|
|
SLAVE_ADDR: i2c_sda = slave_addr[7 - cnt_bit];
|
|
|
|
|
|
DEVICE_ADDR:i2c_sda = device_addr[7 - cnt_bit];
|
|
|
|
|
|
DATA: if((step == 3'd3) || (step == 3'd6))begin
|
|
|
|
|
|
i2c_sda = sda_in;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
i2c_sda = wr_data[7 - cnt_bit];
|
|
|
|
|
|
end
|
|
|
|
|
|
ACK_1, ACK_2, ACK_3:
|
|
|
|
|
|
i2c_sda = 1'b0;
|
|
|
|
|
|
WAIT: i2c_sda = 1'b0;
|
|
|
|
|
|
NACK: i2c_sda = 1'b1;//主机给从机发1
|
|
|
|
|
|
STOP: i2c_sda = (cnt_i2c_clk >= 2'd2) ? 1'b1 : 1'b0;
|
|
|
|
|
|
default: i2c_sda = 1'b1;
|
|
|
|
|
|
endcase
|
|
|
|
|
|
end
|
|
|
|
|
|
assign scl = i2c_scl;
|
|
|
|
|
|
always @(posedge i2c_clk or negedge sys_rst_n)begin
|
|
|
|
|
|
if(!sys_rst_n)begin
|
|
|
|
|
|
po_data <= 8'h0;
|
|
|
|
|
|
end
|
|
|
|
|
|
else if((state_c == DATA) && (step == 3'd6) && (cnt_bit == 3'd7) && (cnt_i2c_clk == 2'd3) && (recv_data != 8'h00))begin
|
|
|
|
|
|
po_data <= recv_data;
|
|
|
|
|
|
end
|
|
|
|
|
|
else begin
|
|
|
|
|
|
po_data <= 8'h0;
|
|
|
|
|
|
end
|
|
|
|
|
|
end
|
|
|
|
|
|
endmodule
|
