software tools update
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# Copyright (C) 2018 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details.
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# Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
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# File: C:\Users\Stark-lin\Desktop\gesture_tiktok\hardware\rtl\gesture_tiktok.tcl
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# Generated on: Tue May 21 08:37:41 2024
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package require ::quartus::project
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set_location_assignment PIN_M12 -to sda
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set_location_assignment PIN_N14 -to scl
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set_location_assignment PIN_E1 -to sys_clk
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set_location_assignment PIN_E15 -to sys_rst_n
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set_location_assignment PIN_G1 -to tx
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set_location_assignment PIN_G15 -to led[0]
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set_location_assignment PIN_F16 -to led[1]
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set_location_assignment PIN_F15 -to led[2]
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set_location_assignment PIN_D16 -to led[3]
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File diff suppressed because it is too large
Load Diff
@ -1,19 +1,19 @@
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module led_ctrl(
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input wire sys_clk ,
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input wire sys_rst_n ,
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input wire [7: 0] po_data ,
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output reg [3: 0] led
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);
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wire [3: 0] data;
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assign data = po_data[3: 0];
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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led <= 4'b0000;
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end
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else begin
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led <= data;
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end
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end
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module led_ctrl(
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input wire sys_clk ,
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input wire sys_rst_n ,
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input wire [7: 0] po_data ,
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output reg [3: 0] led
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);
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wire [3: 0] data;
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assign data = po_data[3: 0];
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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led <= 4'b0000;
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end
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else begin
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led <= data;
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end
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end
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endmodule
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@ -1,86 +1,86 @@
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module paj7620_cfg(
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input wire i2c_clk ,
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input wire sys_rst_n ,
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input wire cfg_start ,
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input wire [2: 0] step ,
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output reg [5: 0] cfg_num ,
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output wire [15: 0] cfg_data ,
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output reg i2c_start
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);
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wire [15: 0] cfg_data_reg[50: 0];
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always @(posedge i2c_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cfg_num <= 6'd0;
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end
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else if((cfg_start == 1'b1) && (step == 3'd4))begin
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cfg_num <= cfg_num + 1'd1;
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end
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else begin
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cfg_num <= cfg_num;
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end
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end
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always @(posedge i2c_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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i2c_start <= 1'b0;
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end
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else if((cfg_data == 1'b1) && (step == 3'd4))begin
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i2c_start <= 1'b1;
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end
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else begin
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i2c_start <= 1'b0;
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end
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end
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assign cfg_data = (step == 3'd4) ? cfg_data_reg[cfg_num - 1]:16'h0;
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assign cfg_data_reg[00] = {8'hEF,8'h00};
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assign cfg_data_reg[01] = {8'h37,8'h07};
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assign cfg_data_reg[02] = {8'h38,8'h17};
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assign cfg_data_reg[03] = {8'h39,8'h06};
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assign cfg_data_reg[04] = {8'h42,8'h01};
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assign cfg_data_reg[05] = {8'h46,8'h2D};
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assign cfg_data_reg[06] = {8'h47,8'h0F};
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assign cfg_data_reg[07] = {8'h48,8'h3C};
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assign cfg_data_reg[08] = {8'h49,8'h00};
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assign cfg_data_reg[09] = {8'h4A,8'h1E};
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assign cfg_data_reg[10] = {8'h4C,8'h20};
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assign cfg_data_reg[11] = {8'h51,8'h10};
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assign cfg_data_reg[12] = {8'h5E,8'h10};
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assign cfg_data_reg[13] = {8'h60,8'h27};
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assign cfg_data_reg[14] = {8'h80,8'h42};
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assign cfg_data_reg[15] = {8'h81,8'h44};
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assign cfg_data_reg[16] = {8'h82,8'h04};
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assign cfg_data_reg[17] = {8'h8B,8'h01};
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assign cfg_data_reg[18] = {8'h90,8'h06};
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assign cfg_data_reg[19] = {8'h95,8'h0A};
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assign cfg_data_reg[20] = {8'h96,8'h0C};
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assign cfg_data_reg[21] = {8'h97,8'h05};
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assign cfg_data_reg[22] = {8'h9A,8'h14};
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assign cfg_data_reg[23] = {8'h9C,8'h3F};
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assign cfg_data_reg[24] = {8'hA5,8'h19};
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assign cfg_data_reg[25] = {8'hCC,8'h19};
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assign cfg_data_reg[26] = {8'hCD,8'h0B};
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assign cfg_data_reg[27] = {8'hCE,8'h13};
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assign cfg_data_reg[28] = {8'hCF,8'h64};
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assign cfg_data_reg[29] = {8'hD0,8'h21};
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assign cfg_data_reg[30] = {8'hEF,8'h01};
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assign cfg_data_reg[31] = {8'h02,8'h0F};
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assign cfg_data_reg[32] = {8'h03,8'h10};
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assign cfg_data_reg[33] = {8'h04,8'h02};
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assign cfg_data_reg[34] = {8'h25,8'h01};
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assign cfg_data_reg[35] = {8'h27,8'h39};
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assign cfg_data_reg[36] = {8'h28,8'h7F};
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assign cfg_data_reg[37] = {8'h29,8'h08};
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assign cfg_data_reg[38] = {8'h3E,8'hFF};
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assign cfg_data_reg[39] = {8'h5E,8'h3D};
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assign cfg_data_reg[40] = {8'h65,8'h96};
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assign cfg_data_reg[41] = {8'h67,8'h97};
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assign cfg_data_reg[42] = {8'h69,8'hCD};
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assign cfg_data_reg[43] = {8'h6A,8'h01};
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assign cfg_data_reg[44] = {8'h6D,8'h2C};
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assign cfg_data_reg[45] = {8'h6E,8'h01};
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assign cfg_data_reg[46] = {8'h72,8'h01};
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assign cfg_data_reg[47] = {8'h73,8'h35};
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assign cfg_data_reg[48] = {8'h74,8'h00};
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assign cfg_data_reg[49] = {8'h77,8'h01};
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assign cfg_data_reg[50] = {8'hEF,8'h00};
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module paj7620_cfg(
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input wire i2c_clk ,
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input wire sys_rst_n ,
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input wire cfg_start ,
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input wire [2: 0] step ,
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output reg [5: 0] cfg_num ,
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output wire [15: 0] cfg_data ,
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output reg i2c_start
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);
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wire [15: 0] cfg_data_reg[50: 0];
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always @(posedge i2c_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cfg_num <= 6'd0;
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end
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else if((cfg_start == 1'b1) && (step == 3'd4))begin
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cfg_num <= cfg_num + 1'd1;
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end
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else begin
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cfg_num <= cfg_num;
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end
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end
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always @(posedge i2c_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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i2c_start <= 1'b0;
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end
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else if((cfg_data == 1'b1) && (step == 3'd4))begin
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i2c_start <= 1'b1;
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end
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else begin
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i2c_start <= 1'b0;
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end
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end
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assign cfg_data = (step == 3'd4) ? cfg_data_reg[cfg_num - 1]:16'h0;
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assign cfg_data_reg[00] = {8'hEF,8'h00};
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assign cfg_data_reg[01] = {8'h37,8'h07};
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assign cfg_data_reg[02] = {8'h38,8'h17};
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assign cfg_data_reg[03] = {8'h39,8'h06};
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assign cfg_data_reg[04] = {8'h42,8'h01};
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assign cfg_data_reg[05] = {8'h46,8'h2D};
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assign cfg_data_reg[06] = {8'h47,8'h0F};
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assign cfg_data_reg[07] = {8'h48,8'h3C};
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assign cfg_data_reg[08] = {8'h49,8'h00};
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assign cfg_data_reg[09] = {8'h4A,8'h1E};
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assign cfg_data_reg[10] = {8'h4C,8'h20};
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assign cfg_data_reg[11] = {8'h51,8'h10};
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assign cfg_data_reg[12] = {8'h5E,8'h10};
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assign cfg_data_reg[13] = {8'h60,8'h27};
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assign cfg_data_reg[14] = {8'h80,8'h42};
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assign cfg_data_reg[15] = {8'h81,8'h44};
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assign cfg_data_reg[16] = {8'h82,8'h04};
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assign cfg_data_reg[17] = {8'h8B,8'h01};
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assign cfg_data_reg[18] = {8'h90,8'h06};
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assign cfg_data_reg[19] = {8'h95,8'h0A};
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assign cfg_data_reg[20] = {8'h96,8'h0C};
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assign cfg_data_reg[21] = {8'h97,8'h05};
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assign cfg_data_reg[22] = {8'h9A,8'h14};
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assign cfg_data_reg[23] = {8'h9C,8'h3F};
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assign cfg_data_reg[24] = {8'hA5,8'h19};
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assign cfg_data_reg[25] = {8'hCC,8'h19};
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assign cfg_data_reg[26] = {8'hCD,8'h0B};
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assign cfg_data_reg[27] = {8'hCE,8'h13};
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assign cfg_data_reg[28] = {8'hCF,8'h64};
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assign cfg_data_reg[29] = {8'hD0,8'h21};
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assign cfg_data_reg[30] = {8'hEF,8'h01};
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assign cfg_data_reg[31] = {8'h02,8'h0F};
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assign cfg_data_reg[32] = {8'h03,8'h10};
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assign cfg_data_reg[33] = {8'h04,8'h02};
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assign cfg_data_reg[34] = {8'h25,8'h01};
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assign cfg_data_reg[35] = {8'h27,8'h39};
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assign cfg_data_reg[36] = {8'h28,8'h7F};
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assign cfg_data_reg[37] = {8'h29,8'h08};
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assign cfg_data_reg[38] = {8'h3E,8'hFF};
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assign cfg_data_reg[39] = {8'h5E,8'h3D};
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assign cfg_data_reg[40] = {8'h65,8'h96};
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assign cfg_data_reg[41] = {8'h67,8'h97};
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assign cfg_data_reg[42] = {8'h69,8'hCD};
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assign cfg_data_reg[43] = {8'h6A,8'h01};
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assign cfg_data_reg[44] = {8'h6D,8'h2C};
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assign cfg_data_reg[45] = {8'h6E,8'h01};
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assign cfg_data_reg[46] = {8'h72,8'h01};
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assign cfg_data_reg[47] = {8'h73,8'h35};
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assign cfg_data_reg[48] = {8'h74,8'h00};
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assign cfg_data_reg[49] = {8'h77,8'h01};
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assign cfg_data_reg[50] = {8'hEF,8'h00};
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endmodule
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@ -0,0 +1,29 @@
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# Copyright (C) 2018 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details.
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||||
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# Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
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# File: C:\Users\Stark-lin\Desktop\gesture_tiktok\hardware\tcl\gesture_tiktok.tcl
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# Generated on: Tue May 21 08:18:12 2024
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package require ::quartus::project
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set_location_assignment PIN_D8 -to sda
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set_location_assignment PIN_E7 -to scl
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set_location_assignment PIN_E1 -to sys_clk
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set_location_assignment PIN_E15 -to sys_rst_n
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set_location_assignment PIN_G1 -to tx
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set_location_assignment PIN_G15 -to led[0]
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set_location_assignment PIN_F16 -to led[1]
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set_location_assignment PIN_F15 -to led[2]
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set_location_assignment PIN_D16 -to led[3]
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