diff --git a/hardware/doc/AWC_C4 DVK用户手册.pdf b/hardware/doc/AWC_C4 DVK用户手册.pdf new file mode 100644 index 0000000..5c35373 Binary files /dev/null and b/hardware/doc/AWC_C4 DVK用户手册.pdf differ diff --git a/doc/中文版使用手册.pdf b/hardware/doc/中文版使用手册.pdf similarity index 100% rename from doc/中文版使用手册.pdf rename to hardware/doc/中文版使用手册.pdf diff --git a/doc/唤醒操作波形图.vsdx b/hardware/doc/唤醒操作波形图.vsdx similarity index 100% rename from doc/唤醒操作波形图.vsdx rename to hardware/doc/唤醒操作波形图.vsdx diff --git a/doc/唤醒状态机.vsdx b/hardware/doc/唤醒状态机.vsdx similarity index 100% rename from doc/唤醒状态机.vsdx rename to hardware/doc/唤醒状态机.vsdx diff --git a/doc/基于FPGA的手势识别控制系统设计.pdf b/hardware/doc/基于FPGA的手势识别控制系统设计.pdf similarity index 100% rename from doc/基于FPGA的手势识别控制系统设计.pdf rename to hardware/doc/基于FPGA的手势识别控制系统设计.pdf diff --git a/doc/激活bank0波形图.vsdx b/hardware/doc/激活bank0波形图.vsdx similarity index 100% rename from doc/激活bank0波形图.vsdx rename to hardware/doc/激活bank0波形图.vsdx diff --git a/doc/激活bank0状态机.vsdx b/hardware/doc/激活bank0状态机.vsdx similarity index 100% rename from doc/激活bank0状态机.vsdx rename to hardware/doc/激活bank0状态机.vsdx diff --git a/doc/英文版数据手册.pdf b/hardware/doc/英文版数据手册.pdf similarity index 100% rename from doc/英文版数据手册.pdf rename to hardware/doc/英文版数据手册.pdf diff --git a/doc/计数分频.vsdx b/hardware/doc/计数分频.vsdx similarity index 100% rename from doc/计数分频.vsdx rename to hardware/doc/计数分频.vsdx diff --git a/doc/读取0x00波形图.vsdx b/hardware/doc/读取0x00波形图.vsdx similarity index 100% rename from doc/读取0x00波形图.vsdx rename to hardware/doc/读取0x00波形图.vsdx diff --git a/doc/读取0x00状态机.vsdx b/hardware/doc/读取0x00状态机.vsdx similarity index 100% rename from doc/读取0x00状态机.vsdx rename to hardware/doc/读取0x00状态机.vsdx diff --git a/doc/读取0x43波形图.vsdx b/hardware/doc/读取0x43波形图.vsdx similarity index 100% rename from doc/读取0x43波形图.vsdx rename to hardware/doc/读取0x43波形图.vsdx diff --git a/doc/读取0x43状态机.vsdx b/hardware/doc/读取0x43状态机.vsdx similarity index 100% rename from doc/读取0x43状态机.vsdx rename to hardware/doc/读取0x43状态机.vsdx diff --git a/doc/配置0x00波形图.vsdx b/hardware/doc/配置0x00波形图.vsdx similarity index 100% rename from doc/配置0x00波形图.vsdx rename to hardware/doc/配置0x00波形图.vsdx diff --git a/doc/配置0x00状态机.vsdx b/hardware/doc/配置0x00状态机.vsdx similarity index 100% rename from doc/配置0x00状态机.vsdx rename to hardware/doc/配置0x00状态机.vsdx diff --git a/doc/配置0x43波形图.vsdx b/hardware/doc/配置0x43波形图.vsdx similarity index 100% rename from doc/配置0x43波形图.vsdx rename to hardware/doc/配置0x43波形图.vsdx diff --git a/doc/配置0x43状态机.vsdx b/hardware/doc/配置0x43状态机.vsdx similarity index 100% rename from doc/配置0x43状态机.vsdx rename to hardware/doc/配置0x43状态机.vsdx diff --git a/doc/配置51寄存器波形图.vsdx b/hardware/doc/配置51寄存器波形图.vsdx similarity index 100% rename from doc/配置51寄存器波形图.vsdx rename to hardware/doc/配置51寄存器波形图.vsdx diff --git a/doc/配置51寄存器状态机.vsdx b/hardware/doc/配置51寄存器状态机.vsdx similarity index 100% rename from doc/配置51寄存器状态机.vsdx rename to hardware/doc/配置51寄存器状态机.vsdx diff --git a/rtl/ges_recognize.v b/hardware/rtl/ges_recognize.v similarity index 95% rename from rtl/ges_recognize.v rename to hardware/rtl/ges_recognize.v index 815f678..0f28646 100644 --- a/rtl/ges_recognize.v +++ b/hardware/rtl/ges_recognize.v @@ -1,64 +1,64 @@ -module ges_recognize( - input wire sys_clk , - input wire sys_rst_n , - - output wire scl , - inout wire sda , - output wire [3: 0] led , - output wire tx -); -wire [2: 0] step ; -wire [5: 0] cfg_num ; -wire [15: 0] cfg_data ; -wire cfg_start ; -wire i2c_clk ; -wire i2c_start ; -wire [7: 0] po_data ; -wire tx_vld ; -reg send_flag ; -wire rx_vld ; - -assign rx_vld = po_data != 8'h00; -paj7620_cfg paj7620_cfg_inst( -.i2c_clk (i2c_clk ), -.sys_rst_n (sys_rst_n ), -.cfg_start (cfg_start ), -.step (step ), - -.cfg_num (cfg_num ), -.cfg_data (cfg_data ), -.i2c_start (i2c_start ) -); -i2c_ctrl i2c_ctrl_inst( -.sys_clk (sys_clk ), -.sys_rst_n (sys_rst_n ), -.i2c_start (i2c_start ), -.cfg_num (cfg_num ), -.cfg_data (cfg_data ), - -.cfg_start (cfg_start ), -.step (step ), -.i2c_clk (i2c_clk ), -.scl (scl ), -.sda (sda ), -.po_data (po_data ) - -); -uart_tx uart_tx_inst( -.sys_clk (sys_clk), -.sys_rst_n (sys_rst_n), -.tx_din (po_data),//并行输入，接受模块传入 -.rx_vld (rx_vld),//接受模块，串转并有效信号 - - -.tx_vld (tx_vld), -.tx_dout (tx)//串行输出 -); -led_ctrl led_ctrl_inst( -.sys_clk (sys_clk ), -.sys_rst_n (sys_rst_n ), -.po_data (po_data ), - -.led (led ) -); +module ges_recognize( + input wire sys_clk , + input wire sys_rst_n , + + output wire scl , + inout wire sda , + output wire [3: 0] led , + output wire tx +); +wire [2: 0] step ; +wire [5: 0] cfg_num ; +wire [15: 0] cfg_data ; +wire cfg_start ; +wire i2c_clk ; +wire i2c_start ; +wire [7: 0] po_data ; +wire tx_vld ; +reg send_flag ; +wire rx_vld ; + +assign rx_vld = po_data != 8'h00; +paj7620_cfg paj7620_cfg_inst( +.i2c_clk (i2c_clk ), +.sys_rst_n (sys_rst_n ), +.cfg_start (cfg_start ), +.step (step ), + +.cfg_num (cfg_num ), +.cfg_data (cfg_data ), +.i2c_start (i2c_start ) +); +i2c_ctrl i2c_ctrl_inst( +.sys_clk (sys_clk ), +.sys_rst_n (sys_rst_n ), +.i2c_start (i2c_start ), +.cfg_num (cfg_num ), +.cfg_data (cfg_data ), + +.cfg_start (cfg_start ), +.step (step ), +.i2c_clk (i2c_clk ), +.scl (scl ), +.sda (sda ), +.po_data (po_data ) + +); +uart_tx uart_tx_inst( +.sys_clk (sys_clk), +.sys_rst_n (sys_rst_n), +.tx_din (po_data),//并行输入，接受模块传入 +.rx_vld (rx_vld),//接受模块，串转并有效信号 + + +.tx_vld (tx_vld), +.tx_dout (tx)//串行输出 +); +led_ctrl led_ctrl_inst( +.sys_clk (sys_clk ), +.sys_rst_n (sys_rst_n ), +.po_data (po_data ), + +.led (led ) +); endmodule \ No newline at end of file diff --git a/rtl/ges_recognize.v.bak b/hardware/rtl/ges_recognize.v.bak similarity index 100% rename from rtl/ges_recognize.v.bak rename to hardware/rtl/ges_recognize.v.bak diff --git a/hardware/rtl/gesture_tiktok.tcl b/hardware/rtl/gesture_tiktok.tcl new file mode 100644 index 0000000..ac2c583 --- /dev/null +++ b/hardware/rtl/gesture_tiktok.tcl @@ -0,0 +1,29 @@ +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. + +# Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# File: C:\Users\Stark-lin\Desktop\gesture_tiktok\hardware\rtl\gesture_tiktok.tcl +# Generated on: Tue May 21 08:37:41 2024 + +package require ::quartus::project + +set_location_assignment PIN_M12 -to sda +set_location_assignment PIN_N14 -to scl +set_location_assignment PIN_E1 -to sys_clk +set_location_assignment PIN_E15 -to sys_rst_n +set_location_assignment PIN_G1 -to tx +set_location_assignment PIN_G15 -to led[0] +set_location_assignment PIN_F16 -to led[1] +set_location_assignment PIN_F15 -to led[2] +set_location_assignment PIN_D16 -to led[3] diff --git a/rtl/i2c_ctrl.v b/hardware/rtl/i2c_ctrl.v similarity index 97% rename from rtl/i2c_ctrl.v rename to hardware/rtl/i2c_ctrl.v index 922c468..19faa16 100644 --- a/rtl/i2c_ctrl.v +++ b/hardware/rtl/i2c_ctrl.v @@ -1,754 +1,754 @@ -module i2c_ctrl( - input wire sys_clk , - input wire sys_rst_n , - input wire i2c_start , - input wire [5: 0] cfg_num , - input wire [15: 0] cfg_data , - - output reg cfg_start , - output reg [2: 0] step , - output reg i2c_clk , - output wire scl , - inout wire sda , - output reg [7: 0] po_data - - -); -parameter I2C_CLK_DIV = 5'd24, - MAX = 10'd1000, - SLAVE_ID = 7'h73; -//状态机参数定义 -parameter IDLE = 4'd0, - START = 4'd1, - SLAVE_ADDR = 4'd2, - ACK_1 = 4'd3, - ACK_2 = 4'd4, - ACK_3 = 4'd5, - DEVICE_ADDR = 4'd6, - DATA = 4'd7, - WAIT = 4'd8, - NACK = 4'd9, - STOP = 4'd10; -reg [3: 0] state_c; -reg [3: 0] state_n; -//// - -//i2c时钟计数器 -reg [4: 0] cnt_clk; -///// - -//中间信号定义 -reg [9: 0] cnt_wait ;//1000us -reg skip_en_1 ;//步骤1跳转信号,唤醒 -reg skip_en_2 ;//步骤2跳转信号,激活bank0 -reg skip_en_3 ;//步骤3跳转信号,配置0x00 -reg skip_en_4 ;//步骤4跳转信号,读取0x20 -reg skip_en_5 ;//步骤5跳转信号,配置51寄存器 -reg skip_en_6 ;//步骤6跳转信号,配置0x43 -reg skip_en_7 ;//步骤7跳转信号,读取0x43 -reg [1: 0] cnt_i2c_clk ;//i2c计数器 -reg [2: 0] cnt_bit ;//bit计数器 -reg i2c_end ;//i2c结束信号 -wire sda_en ; -wire sda_in ; -reg i2c_sda ; -reg i2c_scl ; -reg [7: 0] slave_addr ; -reg [7: 0] device_addr ; -reg [7: 0] wr_data ; -reg [7: 0] recv_data ;//接受0x20寄存器 -reg ack ;//接受信号 -reg err_en ;//接受到0x20有误 -//三态门 -assign sda_en = ((state_c == ACK_1) || (state_c == ACK_2) || (state_c == ACK_3) || (state_c == DATA && (step == 3'd3 || step == 3'd6))) ? 1'b0: 1'b1;//发送主机控制从机，接受主机释放 -assign sda_in = sda; -assign sda = (sda_en == 1'b1)? i2c_sda : 1'bz; -//cfg_start -always @(posedge i2c_clk or negedge sys_rst_n)begin - if(!sys_rst_n)begin - cfg_start <= 1'b0; - end - else begin - cfg_start <= i2c_end;//延迟一个时钟输出 - end -end -//i2c驱动时钟设计 -always @(posedge sys_clk or negedge sys_rst_n) begin - if(!sys_rst_n)begin - cnt_clk <= 5'd0; - end - else if(cnt_clk == I2C_CLK_DIV)begin - cnt_clk <= 5'd0; - end - else begin - cnt_clk <= cnt_clk + 1; - end -end - -always @(posedge sys_clk or negedge sys_rst_n) begin - if(!sys_rst_n)begin - i2c_clk <= 1'b1; - end - else if(cnt_clk == I2C_CLK_DIV)begin - i2c_clk <= ~i2c_clk; - end - else begin - i2c_clk <= i2c_clk; - end -end -///////// -//状态机，第一段 -always @(posedge i2c_clk or negedge sys_rst_n) begin - if(!sys_rst_n)begin - state_c <= IDLE; - end - else begin - state_c <= state_n; - end -end -//状态机第二段 -always @(*)begin - case(state_c) - IDLE: if((skip_en_1 == 1'b1) || (skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_4 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1) || (skip_en_7 == 1'b1))begin - state_n = START; - end - else begin - state_n = IDLE; - end - START: if((skip_en_1 == 1'b1) || (skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_4 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1) || (skip_en_7 == 1'b1))begin - state_n = SLAVE_ADDR; - end - else begin - state_n = START; - end - SLAVE_ADDR: if(skip_en_1 == 1'b1)begin - state_n = WAIT; - end - else if((skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_4 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1) || (skip_en_7 == 1'b1))begin - state_n = ACK_1; - end - else begin - state_n = SLAVE_ADDR; - end - ACK_1: if((skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1))begin - state_n = DEVICE_ADDR; - end - else if((skip_en_4 == 1'b1) || (skip_en_7 == 1'b1))begin - state_n = DATA; - end - else begin - state_n = ACK_1; - end - DEVICE_ADDR:if((skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1))begin - state_n = ACK_2; - end - else begin - state_n = DEVICE_ADDR; - end - ACK_2: if((skip_en_2 == 1'b1) || (skip_en_5 == 1'b1))begin - state_n = DATA; - end - else if((skip_en_3 == 1'b1) || (skip_en_6 == 1'b1))begin - state_n = STOP; - end - else begin - state_n = ACK_2; - end - DATA: if((skip_en_2 == 1'b1) || (skip_en_5 == 1'b1))begin - state_n = ACK_3; - end - else if((skip_en_4 == 1'b1) || (skip_en_7 == 1'b1))begin - state_n = NACK; - end - else if(err_en == 1'b1)begin - state_n = IDLE; - end - else begin - state_n = DATA; - end - NACK: if((skip_en_4 == 1'b1) || (skip_en_7 == 1'b1))begin - state_n = STOP; - end - else begin - state_n = NACK; - end - ACK_3: if((skip_en_2 == 1'b1) || (skip_en_5 == 1'b1))begin - state_n = STOP; - end - else begin - state_n = ACK_3; - end - WAIT: if(skip_en_1 == 1'b1)begin - state_n = STOP; - end - else begin - state_n = WAIT; - end - STOP: if((skip_en_1 == 1'b1) || (skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_4 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1) || (skip_en_7 == 1'b1))begin - state_n = IDLE; - end - else begin - state_n = STOP; - end - default: begin - state_n = IDLE; - end - endcase -end -//状态机第三段 -always @(posedge i2c_clk or negedge sys_rst_n)begin - if(!sys_rst_n)begin - cnt_wait <= 10'd0; - skip_en_1 <= 1'b0;//步骤1跳转信号 - skip_en_2 <= 1'b0;//步骤2跳转信号 - skip_en_3 <= 1'b0;//步骤3跳转信号 - skip_en_4 <= 1'b0;//步骤4跳转信号 - skip_en_5 <= 1'b0;//步骤5跳转信号 - skip_en_6 <= 1'b0;//步骤6跳转信号 - skip_en_7 <= 1'b0;//步骤7跳转信号 - step <= 3'd0; - err_en <= 1'b0; - cnt_i2c_clk <= 2'd0; - cnt_bit <= 3'd0; - i2c_end <= 1'b0; - end - else begin - case(state_c) - IDLE: begin - if(cnt_wait == MAX - 1)begin - cnt_wait <= 10'd0; - end - else begin - cnt_wait <= cnt_wait + 1; - end - if((cnt_wait == MAX - 2'd2) && (step == 3'd0))begin - skip_en_1 <= 1'b1; - end - else begin - skip_en_1 <= 1'b0; - end - if((cnt_wait == MAX - 2'd2) && (step == 3'd1))begin - skip_en_2 <= 1'b1; - end - else begin - skip_en_2 <= 1'b0; - end - if((cnt_wait == MAX - 2'd2) && (step == 3'd2))begin - skip_en_3 <= 1'b1; - end - else begin - skip_en_3 <= 1'b0; - end - if((cnt_wait == MAX - 2'd2) && (step == 3'd3))begin - skip_en_4 <= 1'b1; - end - else begin - skip_en_4 <= 1'b0; - end - if((cnt_wait == MAX - 2'd2) && (step == 3'd4))begin - skip_en_5 <= 1'b1; - end - else begin - skip_en_5 <= 1'b0; - end - if((cnt_wait == MAX - 2'd2) && (step == 3'd5))begin - skip_en_6 <= 1'b1; - end - else begin - skip_en_6 <= 1'b0; - end - if((cnt_wait == MAX - 2'd2) && (step == 3'd6))begin - skip_en_7 <= 1'b1; - end - else begin - skip_en_7 <= 1'b0; - end - end - START: begin - cnt_i2c_clk <= cnt_i2c_clk + 1'd1; - if((cnt_i2c_clk == 2'd2) && (step == 3'd0))begin - skip_en_1 <= 1'b1; - end - else begin - skip_en_1 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd1))begin - skip_en_2 <= 1'b1; - end - else begin - skip_en_2 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd2))begin - skip_en_3 <= 1'b1; - end - else begin - skip_en_3 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd3))begin - skip_en_4 <= 1'b1; - end - else begin - skip_en_4 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd4))begin - skip_en_5 <= 1'b1; - end - else begin - skip_en_5 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd5))begin - skip_en_6 <= 1'b1; - end - else begin - skip_en_6 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd6))begin - skip_en_7 <= 1'b1; - end - else begin - skip_en_7 <= 1'b0; - end - end - SLAVE_ADDR: begin - cnt_i2c_clk <= cnt_i2c_clk + 1'd1; - if((cnt_i2c_clk == 2'd2) && (step == 3'd0) && (cnt_bit == 3'd7))begin - skip_en_1 <= 1'b1; - end - else begin - skip_en_1 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd1) && (cnt_bit == 3'd7))begin - skip_en_2 <= 1'b1; - end - else begin - skip_en_2 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd2) && (cnt_bit == 3'd7))begin - skip_en_3 <= 1'b1; - end - else begin - skip_en_3 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd3) && (cnt_bit == 3'd7))begin - skip_en_4 <= 1'b1; - end - else begin - skip_en_4 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd4) && (cnt_bit == 3'd7))begin - skip_en_5 <= 1'b1; - end - else begin - skip_en_5 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd5) && (cnt_bit == 3'd7))begin - skip_en_6 <= 1'b1; - end - else begin - skip_en_6 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd6) && (cnt_bit == 3'd7))begin - skip_en_7 <= 1'b1; - end - else begin - skip_en_7 <= 1'b0; - end - if((cnt_bit == 3'd7) && (cnt_i2c_clk == 2'd3))begin - cnt_bit <= 3'd0; - end - else if(cnt_i2c_clk == 2'd3)begin - cnt_bit <= cnt_bit + 1'd1; - end - else begin - cnt_bit <= cnt_bit; - end - end - ACK_1: begin - cnt_i2c_clk <= cnt_i2c_clk + 1'd1; - if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd1))begin - skip_en_2 <= 1'b1; - end - else begin - skip_en_2 <= 1'b0; - end - if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd2))begin - skip_en_3 <= 1'b1; - end - else begin - skip_en_3 <= 1'b0; - end - if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd3))begin - skip_en_4 <= 1'b1; - end - else begin - skip_en_4 <= 1'b0; - end - if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd4))begin - skip_en_5 <= 1'b1; - end - else begin - skip_en_5 <= 1'b0; - end - if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd5))begin - skip_en_6 <= 1'b1; - end - else begin - skip_en_6 <= 1'b0; - end - if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd6))begin - skip_en_7 <= 1'b1; - end - else begin - skip_en_7 <= 1'b0; - end - end - DEVICE_ADDR:begin - cnt_i2c_clk <= cnt_i2c_clk + 1'b1; - if((cnt_i2c_clk == 2'd3) && (cnt_bit == 3'd7))begin - cnt_bit <= 3'd0; - end - else if(cnt_i2c_clk == 2'd3)begin - cnt_bit <= cnt_bit + 1'b1; - end - else begin - cnt_bit <= cnt_bit; - end - if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd1))begin - skip_en_2 <= 1'b1; - end - else begin - skip_en_2 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd2))begin - skip_en_3 <= 1'b1; - end - else begin - skip_en_3 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd4))begin - skip_en_5 <= 1'b1; - end - else begin - skip_en_5 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd5))begin - skip_en_6 <= 1'b1; - end - else begin - skip_en_6 <= 1'b0; - end - end - ACK_2: begin - cnt_i2c_clk <= cnt_i2c_clk + 1; - if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd1))begin - skip_en_2 <= 1'b1; - end - else begin - skip_en_2 <= 1'b0; - end - if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd2))begin - skip_en_3 <= 1'b1; - end - else begin - skip_en_3 <= 1'b0; - end - if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd4))begin - skip_en_5 <= 1'b1; - end - else begin - skip_en_5 <= 1'b0; - end - if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd5))begin - skip_en_6 <= 1'b1; - end - else begin - skip_en_6 <= 1'b0; - end - end - DATA: begin - cnt_i2c_clk <= cnt_i2c_clk + 1'b1; - if((cnt_i2c_clk == 2'd3) && (cnt_bit == 3'd7))begin - cnt_bit <= 3'd0; - end - else if(cnt_i2c_clk == 2'd3)begin - cnt_bit <= cnt_bit + 1'b1; - end - else begin - cnt_bit <= cnt_bit; - end - if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd1))begin - skip_en_2 <= 1'b1; - end - else begin - skip_en_2 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd3) && (recv_data == 8'h20))begin - skip_en_4 <= 1'b1; - end - else begin - skip_en_4 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd4))begin - skip_en_5 <= 1'b1; - end - else begin - skip_en_5 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd6))begin - skip_en_7 <= 1'b1; - end - else begin - skip_en_7 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd3) && (recv_data != 8'h20))begin - begin - err_en <= 1'b1; - step <= 3'd0; - end - end - else begin - begin - err_en <= 1'b0; - step <= step; - end - end - end - NACK: begin - cnt_i2c_clk <= cnt_i2c_clk + 1; - if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd3))begin - skip_en_4 <= 1'b1; - end - else begin - skip_en_4 <= 1'b0; - end - if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd6))begin - skip_en_7 <= 1'b1; - end - else begin - skip_en_7 <= 1'b0; - end - end - ACK_3: begin - cnt_i2c_clk <= cnt_i2c_clk + 1; - if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd1))begin - skip_en_2 <= 1'b1; - end - else begin - skip_en_2 <= 1'b0; - end - if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd4))begin - skip_en_5 <= 1'b1; - end - else begin - skip_en_5 <= 1'b0; - end - end - WAIT: begin - if(cnt_wait == MAX - 1'd1)begin - cnt_wait <= 10'd0; - end - else begin - cnt_wait <= cnt_wait + 1'd1; - end - if((cnt_wait == MAX - 2'd2) && (step == 3'd0))begin - skip_en_1 <= 1'b1; - end - else begin - skip_en_1 <= 1'b0; - end - end - STOP: begin - cnt_i2c_clk <= cnt_i2c_clk + 1'd1; - if((cnt_i2c_clk == 2'd2) && (step == 3'd0))begin - skip_en_1 <= 1'b1; - end - else begin - skip_en_1 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd1))begin - skip_en_2 <= 1'b1; - end - else begin - skip_en_2 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd2))begin - skip_en_3 <= 1'b1; - end - else begin - skip_en_3 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd3))begin - skip_en_4 <= 1'b1; - end - else begin - skip_en_4 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd4))begin - skip_en_5 <= 1'b1; - end - else begin - skip_en_5 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd5))begin - skip_en_6 <= 1'b1; - end - else begin - skip_en_6 <= 1'b0; - end - if((cnt_i2c_clk == 2'd2) && (step == 3'd6))begin - skip_en_7 <= 1'b1; - end - else begin - skip_en_7 <= 1'b0; - end - if(cnt_i2c_clk == 2'd2)begin - i2c_end <= 1'b1; - end - else begin - i2c_end <= 1'b0; - end - if((i2c_end == 1'b1) && ((step <= 3'd3) || step == 3'd5))begin - step <= step + 1'd1; - end - else if((i2c_end == 1'b1) && (step == 3'd4) && (cfg_num == 6'd51))begin - step <= step + 1'd1; - end - else begin - step <= step; - end - end - default: begin - cnt_wait <= 10'd0; - skip_en_1 <= 1'b0; - skip_en_2 <= 1'b0; - skip_en_3 <= 1'b0; - skip_en_4 <= 1'b0; - skip_en_5 <= 1'b0; - skip_en_6 <= 1'b0; - skip_en_7 <= 1'b0; - err_en <= 1'b0; - step <= step; - cnt_i2c_clk <= 2'd0; - cnt_bit <= 3'd0; - i2c_end <= 1'b0; - end - endcase - end -end -//recv_data -always @(posedge i2c_clk or negedge sys_rst_n)begin - if(!sys_rst_n)begin - recv_data <= 8'h0; - end - else begin - case(state_c) - DATA: begin - if((cnt_i2c_clk == 2'd1) && ((step == 3'd3) || (step == 3'd6)))begin - recv_data <= {recv_data[6:0], sda_in}; - end - else begin - recv_data <= recv_data; - end - end - default: recv_data <= recv_data; - endcase - end -end -//ack -always @(*)begin - case(state_c) - ACK_1, ACK_2, ACK_3: ack = ~sda_in; - NACK: ack = i2c_sda;//主机发送NACK - default: ack = 1'b0; - endcase -end -//step -always @(*)begin - case(step) - 3'd0: begin - slave_addr = {SLAVE_ID, 1'b0}; - device_addr = 8'h0; - wr_data = 8'h0; - end - 3'd1: begin - slave_addr = {SLAVE_ID, 1'b0}; - device_addr= {8'hef}; - wr_data = {8'h00}; - end - 3'd2: begin - slave_addr = {SLAVE_ID, 1'b0}; - device_addr= {8'h00}; - wr_data = {8'h00}; - end - 3'd3: begin - slave_addr = {SLAVE_ID, 1'b1};//读取 - device_addr= {8'h00}; - wr_data = {8'h00}; - end - 3'd4: begin - slave_addr = {SLAVE_ID, 1'b0}; - device_addr= cfg_data[15: 8]; - wr_data = cfg_data[7: 0]; - end - 3'd5: begin - slave_addr = {SLAVE_ID, 1'b0};//配置 - device_addr= 8'h43; - wr_data = 8'h00; - end - 3'd6: begin - slave_addr = {SLAVE_ID, 1'b1};//读取 - device_addr= 8'h43; - wr_data = 8'h00; - end - default:begin - slave_addr = 8'h0; - device_addr = 8'h0; - wr_data = 8'h0; - end - endcase -end -//i2c_scl -always @(*)begin - case(state_c) - IDLE: i2c_scl = 1'b1; - START: i2c_scl = (cnt_i2c_clk <= 2'd2) ? 1'b1 : 1'b0; - SLAVE_ADDR, DEVICE_ADDR, DATA, ACK_1, ACK_2, ACK_3, NACK: - i2c_scl = ((cnt_i2c_clk == 2'd1) || (cnt_i2c_clk == 2'd2)) ? 1'b1 : 1'b0; - WAIT: i2c_scl = 1'b0; - STOP: i2c_scl = (cnt_i2c_clk >= 2'd1) ? 1'b1 : 1'b0; - endcase -end -//i2c_sda -always @(*)begin - case(state_c) - IDLE: i2c_sda = 1'b1; - START: i2c_sda = (cnt_i2c_clk > 2'd1) ? 1'b0 : 1'b1; - SLAVE_ADDR: i2c_sda = slave_addr[7 - cnt_bit]; - DEVICE_ADDR:i2c_sda = device_addr[7 - cnt_bit]; - DATA: if((step == 3'd3) || (step == 3'd6))begin - i2c_sda = sda_in; - end - else begin - i2c_sda = wr_data[7 - cnt_bit]; - end - ACK_1, ACK_2, ACK_3: - i2c_sda = 1'b0; - WAIT: i2c_sda = 1'b0; - NACK: i2c_sda = 1'b1;//主机给从机发1 - STOP: i2c_sda = (cnt_i2c_clk >= 2'd2) ? 1'b1 : 1'b0; - default: i2c_sda = 1'b1; - endcase -end -assign scl = i2c_scl; -always @(posedge i2c_clk or negedge sys_rst_n)begin - if(!sys_rst_n)begin - po_data <= 8'h0; - end - else if((state_c == DATA) && (step == 3'd6) && (cnt_bit == 3'd7) && (cnt_i2c_clk == 2'd3) && (recv_data != 8'h00))begin - po_data <= recv_data; - end - else begin - po_data <= 8'h0; - end -end +module i2c_ctrl( + input wire sys_clk , + input wire sys_rst_n , + input wire i2c_start , + input wire [5: 0] cfg_num , + input wire [15: 0] cfg_data , + + output reg cfg_start , + output reg [2: 0] step , + output reg i2c_clk , + output wire scl , + inout wire sda , + output reg [7: 0] po_data + + +); +parameter I2C_CLK_DIV = 5'd24, + MAX = 10'd1000, + SLAVE_ID = 7'h73; +//状态机参数定义 +parameter IDLE = 4'd0, + START = 4'd1, + SLAVE_ADDR = 4'd2, + ACK_1 = 4'd3, + ACK_2 = 4'd4, + ACK_3 = 4'd5, + DEVICE_ADDR = 4'd6, + DATA = 4'd7, + WAIT = 4'd8, + NACK = 4'd9, + STOP = 4'd10; +reg [3: 0] state_c; +reg [3: 0] state_n; +//// + +//i2c时钟计数器 +reg [4: 0] cnt_clk; +///// + +//中间信号定义 +reg [9: 0] cnt_wait ;//1000us +reg skip_en_1 ;//步骤1跳转信号,唤醒 +reg skip_en_2 ;//步骤2跳转信号,激活bank0 +reg skip_en_3 ;//步骤3跳转信号,配置0x00 +reg skip_en_4 ;//步骤4跳转信号,读取0x20 +reg skip_en_5 ;//步骤5跳转信号,配置51寄存器 +reg skip_en_6 ;//步骤6跳转信号,配置0x43 +reg skip_en_7 ;//步骤7跳转信号,读取0x43 +reg [1: 0] cnt_i2c_clk ;//i2c计数器 +reg [2: 0] cnt_bit ;//bit计数器 +reg i2c_end ;//i2c结束信号 +wire sda_en ; +wire sda_in ; +reg i2c_sda ; +reg i2c_scl ; +reg [7: 0] slave_addr ; +reg [7: 0] device_addr ; +reg [7: 0] wr_data ; +reg [7: 0] recv_data ;//接受0x20寄存器 +reg ack ;//接受信号 +reg err_en ;//接受到0x20有误 +//三态门 +assign sda_en = ((state_c == ACK_1) || (state_c == ACK_2) || (state_c == ACK_3) || (state_c == DATA && (step == 3'd3 || step == 3'd6))) ? 1'b0: 1'b1;//发送主机控制从机，接受主机释放 +assign sda_in = sda; +assign sda = (sda_en == 1'b1)? i2c_sda : 1'bz; +//cfg_start +always @(posedge i2c_clk or negedge sys_rst_n)begin + if(!sys_rst_n)begin + cfg_start <= 1'b0; + end + else begin + cfg_start <= i2c_end;//延迟一个时钟输出 + end +end +//i2c驱动时钟设计 +always @(posedge sys_clk or negedge sys_rst_n) begin + if(!sys_rst_n)begin + cnt_clk <= 5'd0; + end + else if(cnt_clk == I2C_CLK_DIV)begin + cnt_clk <= 5'd0; + end + else begin + cnt_clk <= cnt_clk + 1; + end +end + +always @(posedge sys_clk or negedge sys_rst_n) begin + if(!sys_rst_n)begin + i2c_clk <= 1'b1; + end + else if(cnt_clk == I2C_CLK_DIV)begin + i2c_clk <= ~i2c_clk; + end + else begin + i2c_clk <= i2c_clk; + end +end +///////// +//状态机，第一段 +always @(posedge i2c_clk or negedge sys_rst_n) begin + if(!sys_rst_n)begin + state_c <= IDLE; + end + else begin + state_c <= state_n; + end +end +//状态机第二段 +always @(*)begin + case(state_c) + IDLE: if((skip_en_1 == 1'b1) || (skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_4 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1) || (skip_en_7 == 1'b1))begin + state_n = START; + end + else begin + state_n = IDLE; + end + START: if((skip_en_1 == 1'b1) || (skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_4 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1) || (skip_en_7 == 1'b1))begin + state_n = SLAVE_ADDR; + end + else begin + state_n = START; + end + SLAVE_ADDR: if(skip_en_1 == 1'b1)begin + state_n = WAIT; + end + else if((skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_4 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1) || (skip_en_7 == 1'b1))begin + state_n = ACK_1; + end + else begin + state_n = SLAVE_ADDR; + end + ACK_1: if((skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1))begin + state_n = DEVICE_ADDR; + end + else if((skip_en_4 == 1'b1) || (skip_en_7 == 1'b1))begin + state_n = DATA; + end + else begin + state_n = ACK_1; + end + DEVICE_ADDR:if((skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1))begin + state_n = ACK_2; + end + else begin + state_n = DEVICE_ADDR; + end + ACK_2: if((skip_en_2 == 1'b1) || (skip_en_5 == 1'b1))begin + state_n = DATA; + end + else if((skip_en_3 == 1'b1) || (skip_en_6 == 1'b1))begin + state_n = STOP; + end + else begin + state_n = ACK_2; + end + DATA: if((skip_en_2 == 1'b1) || (skip_en_5 == 1'b1))begin + state_n = ACK_3; + end + else if((skip_en_4 == 1'b1) || (skip_en_7 == 1'b1))begin + state_n = NACK; + end + else if(err_en == 1'b1)begin + state_n = IDLE; + end + else begin + state_n = DATA; + end + NACK: if((skip_en_4 == 1'b1) || (skip_en_7 == 1'b1))begin + state_n = STOP; + end + else begin + state_n = NACK; + end + ACK_3: if((skip_en_2 == 1'b1) || (skip_en_5 == 1'b1))begin + state_n = STOP; + end + else begin + state_n = ACK_3; + end + WAIT: if(skip_en_1 == 1'b1)begin + state_n = STOP; + end + else begin + state_n = WAIT; + end + STOP: if((skip_en_1 == 1'b1) || (skip_en_2 == 1'b1) || (skip_en_3 == 1'b1) || (skip_en_4 == 1'b1) || (skip_en_5 == 1'b1) || (skip_en_6 == 1'b1) || (skip_en_7 == 1'b1))begin + state_n = IDLE; + end + else begin + state_n = STOP; + end + default: begin + state_n = IDLE; + end + endcase +end +//状态机第三段 +always @(posedge i2c_clk or negedge sys_rst_n)begin + if(!sys_rst_n)begin + cnt_wait <= 10'd0; + skip_en_1 <= 1'b0;//步骤1跳转信号 + skip_en_2 <= 1'b0;//步骤2跳转信号 + skip_en_3 <= 1'b0;//步骤3跳转信号 + skip_en_4 <= 1'b0;//步骤4跳转信号 + skip_en_5 <= 1'b0;//步骤5跳转信号 + skip_en_6 <= 1'b0;//步骤6跳转信号 + skip_en_7 <= 1'b0;//步骤7跳转信号 + step <= 3'd0; + err_en <= 1'b0; + cnt_i2c_clk <= 2'd0; + cnt_bit <= 3'd0; + i2c_end <= 1'b0; + end + else begin + case(state_c) + IDLE: begin + if(cnt_wait == MAX - 1)begin + cnt_wait <= 10'd0; + end + else begin + cnt_wait <= cnt_wait + 1; + end + if((cnt_wait == MAX - 2'd2) && (step == 3'd0))begin + skip_en_1 <= 1'b1; + end + else begin + skip_en_1 <= 1'b0; + end + if((cnt_wait == MAX - 2'd2) && (step == 3'd1))begin + skip_en_2 <= 1'b1; + end + else begin + skip_en_2 <= 1'b0; + end + if((cnt_wait == MAX - 2'd2) && (step == 3'd2))begin + skip_en_3 <= 1'b1; + end + else begin + skip_en_3 <= 1'b0; + end + if((cnt_wait == MAX - 2'd2) && (step == 3'd3))begin + skip_en_4 <= 1'b1; + end + else begin + skip_en_4 <= 1'b0; + end + if((cnt_wait == MAX - 2'd2) && (step == 3'd4))begin + skip_en_5 <= 1'b1; + end + else begin + skip_en_5 <= 1'b0; + end + if((cnt_wait == MAX - 2'd2) && (step == 3'd5))begin + skip_en_6 <= 1'b1; + end + else begin + skip_en_6 <= 1'b0; + end + if((cnt_wait == MAX - 2'd2) && (step == 3'd6))begin + skip_en_7 <= 1'b1; + end + else begin + skip_en_7 <= 1'b0; + end + end + START: begin + cnt_i2c_clk <= cnt_i2c_clk + 1'd1; + if((cnt_i2c_clk == 2'd2) && (step == 3'd0))begin + skip_en_1 <= 1'b1; + end + else begin + skip_en_1 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd1))begin + skip_en_2 <= 1'b1; + end + else begin + skip_en_2 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd2))begin + skip_en_3 <= 1'b1; + end + else begin + skip_en_3 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd3))begin + skip_en_4 <= 1'b1; + end + else begin + skip_en_4 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd4))begin + skip_en_5 <= 1'b1; + end + else begin + skip_en_5 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd5))begin + skip_en_6 <= 1'b1; + end + else begin + skip_en_6 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd6))begin + skip_en_7 <= 1'b1; + end + else begin + skip_en_7 <= 1'b0; + end + end + SLAVE_ADDR: begin + cnt_i2c_clk <= cnt_i2c_clk + 1'd1; + if((cnt_i2c_clk == 2'd2) && (step == 3'd0) && (cnt_bit == 3'd7))begin + skip_en_1 <= 1'b1; + end + else begin + skip_en_1 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd1) && (cnt_bit == 3'd7))begin + skip_en_2 <= 1'b1; + end + else begin + skip_en_2 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd2) && (cnt_bit == 3'd7))begin + skip_en_3 <= 1'b1; + end + else begin + skip_en_3 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd3) && (cnt_bit == 3'd7))begin + skip_en_4 <= 1'b1; + end + else begin + skip_en_4 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd4) && (cnt_bit == 3'd7))begin + skip_en_5 <= 1'b1; + end + else begin + skip_en_5 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd5) && (cnt_bit == 3'd7))begin + skip_en_6 <= 1'b1; + end + else begin + skip_en_6 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd6) && (cnt_bit == 3'd7))begin + skip_en_7 <= 1'b1; + end + else begin + skip_en_7 <= 1'b0; + end + if((cnt_bit == 3'd7) && (cnt_i2c_clk == 2'd3))begin + cnt_bit <= 3'd0; + end + else if(cnt_i2c_clk == 2'd3)begin + cnt_bit <= cnt_bit + 1'd1; + end + else begin + cnt_bit <= cnt_bit; + end + end + ACK_1: begin + cnt_i2c_clk <= cnt_i2c_clk + 1'd1; + if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd1))begin + skip_en_2 <= 1'b1; + end + else begin + skip_en_2 <= 1'b0; + end + if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd2))begin + skip_en_3 <= 1'b1; + end + else begin + skip_en_3 <= 1'b0; + end + if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd3))begin + skip_en_4 <= 1'b1; + end + else begin + skip_en_4 <= 1'b0; + end + if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd4))begin + skip_en_5 <= 1'b1; + end + else begin + skip_en_5 <= 1'b0; + end + if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd5))begin + skip_en_6 <= 1'b1; + end + else begin + skip_en_6 <= 1'b0; + end + if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd6))begin + skip_en_7 <= 1'b1; + end + else begin + skip_en_7 <= 1'b0; + end + end + DEVICE_ADDR:begin + cnt_i2c_clk <= cnt_i2c_clk + 1'b1; + if((cnt_i2c_clk == 2'd3) && (cnt_bit == 3'd7))begin + cnt_bit <= 3'd0; + end + else if(cnt_i2c_clk == 2'd3)begin + cnt_bit <= cnt_bit + 1'b1; + end + else begin + cnt_bit <= cnt_bit; + end + if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd1))begin + skip_en_2 <= 1'b1; + end + else begin + skip_en_2 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd2))begin + skip_en_3 <= 1'b1; + end + else begin + skip_en_3 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd4))begin + skip_en_5 <= 1'b1; + end + else begin + skip_en_5 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd5))begin + skip_en_6 <= 1'b1; + end + else begin + skip_en_6 <= 1'b0; + end + end + ACK_2: begin + cnt_i2c_clk <= cnt_i2c_clk + 1; + if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd1))begin + skip_en_2 <= 1'b1; + end + else begin + skip_en_2 <= 1'b0; + end + if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd2))begin + skip_en_3 <= 1'b1; + end + else begin + skip_en_3 <= 1'b0; + end + if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd4))begin + skip_en_5 <= 1'b1; + end + else begin + skip_en_5 <= 1'b0; + end + if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd5))begin + skip_en_6 <= 1'b1; + end + else begin + skip_en_6 <= 1'b0; + end + end + DATA: begin + cnt_i2c_clk <= cnt_i2c_clk + 1'b1; + if((cnt_i2c_clk == 2'd3) && (cnt_bit == 3'd7))begin + cnt_bit <= 3'd0; + end + else if(cnt_i2c_clk == 2'd3)begin + cnt_bit <= cnt_bit + 1'b1; + end + else begin + cnt_bit <= cnt_bit; + end + if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd1))begin + skip_en_2 <= 1'b1; + end + else begin + skip_en_2 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd3) && (recv_data == 8'h20))begin + skip_en_4 <= 1'b1; + end + else begin + skip_en_4 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd4))begin + skip_en_5 <= 1'b1; + end + else begin + skip_en_5 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd6))begin + skip_en_7 <= 1'b1; + end + else begin + skip_en_7 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd3) && (recv_data != 8'h20))begin + begin + err_en <= 1'b1; + step <= 3'd0; + end + end + else begin + begin + err_en <= 1'b0; + step <= step; + end + end + end + NACK: begin + cnt_i2c_clk <= cnt_i2c_clk + 1; + if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd3))begin + skip_en_4 <= 1'b1; + end + else begin + skip_en_4 <= 1'b0; + end + if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd6))begin + skip_en_7 <= 1'b1; + end + else begin + skip_en_7 <= 1'b0; + end + end + ACK_3: begin + cnt_i2c_clk <= cnt_i2c_clk + 1; + if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd1))begin + skip_en_2 <= 1'b1; + end + else begin + skip_en_2 <= 1'b0; + end + if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd4))begin + skip_en_5 <= 1'b1; + end + else begin + skip_en_5 <= 1'b0; + end + end + WAIT: begin + if(cnt_wait == MAX - 1'd1)begin + cnt_wait <= 10'd0; + end + else begin + cnt_wait <= cnt_wait + 1'd1; + end + if((cnt_wait == MAX - 2'd2) && (step == 3'd0))begin + skip_en_1 <= 1'b1; + end + else begin + skip_en_1 <= 1'b0; + end + end + STOP: begin + cnt_i2c_clk <= cnt_i2c_clk + 1'd1; + if((cnt_i2c_clk == 2'd2) && (step == 3'd0))begin + skip_en_1 <= 1'b1; + end + else begin + skip_en_1 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd1))begin + skip_en_2 <= 1'b1; + end + else begin + skip_en_2 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd2))begin + skip_en_3 <= 1'b1; + end + else begin + skip_en_3 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd3))begin + skip_en_4 <= 1'b1; + end + else begin + skip_en_4 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd4))begin + skip_en_5 <= 1'b1; + end + else begin + skip_en_5 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd5))begin + skip_en_6 <= 1'b1; + end + else begin + skip_en_6 <= 1'b0; + end + if((cnt_i2c_clk == 2'd2) && (step == 3'd6))begin + skip_en_7 <= 1'b1; + end + else begin + skip_en_7 <= 1'b0; + end + if(cnt_i2c_clk == 2'd2)begin + i2c_end <= 1'b1; + end + else begin + i2c_end <= 1'b0; + end + if((i2c_end == 1'b1) && ((step <= 3'd3) || step == 3'd5))begin + step <= step + 1'd1; + end + else if((i2c_end == 1'b1) && (step == 3'd4) && (cfg_num == 6'd51))begin + step <= step + 1'd1; + end + else begin + step <= step; + end + end + default: begin + cnt_wait <= 10'd0; + skip_en_1 <= 1'b0; + skip_en_2 <= 1'b0; + skip_en_3 <= 1'b0; + skip_en_4 <= 1'b0; + skip_en_5 <= 1'b0; + skip_en_6 <= 1'b0; + skip_en_7 <= 1'b0; + err_en <= 1'b0; + step <= step; + cnt_i2c_clk <= 2'd0; + cnt_bit <= 3'd0; + i2c_end <= 1'b0; + end + endcase + end +end +//recv_data +always @(posedge i2c_clk or negedge sys_rst_n)begin + if(!sys_rst_n)begin + recv_data <= 8'h0; + end + else begin + case(state_c) + DATA: begin + if((cnt_i2c_clk == 2'd1) && ((step == 3'd3) || (step == 3'd6)))begin + recv_data <= {recv_data[6:0], sda_in}; + end + else begin + recv_data <= recv_data; + end + end + default: recv_data <= recv_data; + endcase + end +end +//ack +always @(*)begin + case(state_c) + ACK_1, ACK_2, ACK_3: ack = ~sda_in; + NACK: ack = i2c_sda;//主机发送NACK + default: ack = 1'b0; + endcase +end +//step +always @(*)begin + case(step) + 3'd0: begin + slave_addr = {SLAVE_ID, 1'b0}; + device_addr = 8'h0; + wr_data = 8'h0; + end + 3'd1: begin + slave_addr = {SLAVE_ID, 1'b0}; + device_addr= {8'hef}; + wr_data = {8'h00}; + end + 3'd2: begin + slave_addr = {SLAVE_ID, 1'b0}; + device_addr= {8'h00}; + wr_data = {8'h00}; + end + 3'd3: begin + slave_addr = {SLAVE_ID, 1'b1};//读取 + device_addr= {8'h00}; + wr_data = {8'h00}; + end + 3'd4: begin + slave_addr = {SLAVE_ID, 1'b0}; + device_addr= cfg_data[15: 8]; + wr_data = cfg_data[7: 0]; + end + 3'd5: begin + slave_addr = {SLAVE_ID, 1'b0};//配置 + device_addr= 8'h43; + wr_data = 8'h00; + end + 3'd6: begin + slave_addr = {SLAVE_ID, 1'b1};//读取 + device_addr= 8'h43; + wr_data = 8'h00; + end + default:begin + slave_addr = 8'h0; + device_addr = 8'h0; + wr_data = 8'h0; + end + endcase +end +//i2c_scl +always @(*)begin + case(state_c) + IDLE: i2c_scl = 1'b1; + START: i2c_scl = (cnt_i2c_clk <= 2'd2) ? 1'b1 : 1'b0; + SLAVE_ADDR, DEVICE_ADDR, DATA, ACK_1, ACK_2, ACK_3, NACK: + i2c_scl = ((cnt_i2c_clk == 2'd1) || (cnt_i2c_clk == 2'd2)) ? 1'b1 : 1'b0; + WAIT: i2c_scl = 1'b0; + STOP: i2c_scl = (cnt_i2c_clk >= 2'd1) ? 1'b1 : 1'b0; + endcase +end +//i2c_sda +always @(*)begin + case(state_c) + IDLE: i2c_sda = 1'b1; + START: i2c_sda = (cnt_i2c_clk > 2'd1) ? 1'b0 : 1'b1; + SLAVE_ADDR: i2c_sda = slave_addr[7 - cnt_bit]; + DEVICE_ADDR:i2c_sda = device_addr[7 - cnt_bit]; + DATA: if((step == 3'd3) || (step == 3'd6))begin + i2c_sda = sda_in; + end + else begin + i2c_sda = wr_data[7 - cnt_bit]; + end + ACK_1, ACK_2, ACK_3: + i2c_sda = 1'b0; + WAIT: i2c_sda = 1'b0; + NACK: i2c_sda = 1'b1;//主机给从机发1 + STOP: i2c_sda = (cnt_i2c_clk >= 2'd2) ? 1'b1 : 1'b0; + default: i2c_sda = 1'b1; + endcase +end +assign scl = i2c_scl; +always @(posedge i2c_clk or negedge sys_rst_n)begin + if(!sys_rst_n)begin + po_data <= 8'h0; + end + else if((state_c == DATA) && (step == 3'd6) && (cnt_bit == 3'd7) && (cnt_i2c_clk == 2'd3) && (recv_data != 8'h00))begin + po_data <= recv_data; + end + else begin + po_data <= 8'h0; + end +end endmodule \ No newline at end of file diff --git a/rtl/i2c_ctrl.v.bak b/hardware/rtl/i2c_ctrl.v.bak similarity index 96% rename from rtl/i2c_ctrl.v.bak rename to hardware/rtl/i2c_ctrl.v.bak index 8498ee7..60b30b3 100644 --- a/rtl/i2c_ctrl.v.bak +++ b/hardware/rtl/i2c_ctrl.v.bak @@ -1,253 +1,253 @@ -module i2c_ctrl( - input wire sys_clk , - input wire sys_rst_n , - - output wire scl , - inout wire sda - -); -parameter I2C_CLK_DIV = 5'd24, - MAX = 10'd1000, - SLAVE_ID = 7'h73; -//状态机参数定义 -parameter IDLE = 3'd0, - START = 3'd1, - SLAVE_ADDR= 3'd2, - WAIT = 3'd3, - STOP = 3'd4; -reg [2: 0] state_c; -reg [2: 0] state_n; -//// - -//i2c时钟计数器 -reg [4: 0] cnt_clk; -reg i2c_clk; -///// - -//中间信号定义 -reg [9: 0] cnt_wait ;//1000us -reg skip_en_1 ;//跳转信号 -reg [2: 0] step ;//步骤 -reg [1: 0] cnt_i2c_clk ;// -reg [2: 0] cnt_bit ;//bit计数器 -reg i2c_end ;//i2c结束信号 -wire sda_en ; -wire sda_in ; -reg i2c_sda ; -reg i2c_scl ; -reg [7: 0] slave_addr ; -reg [7: 0] device_addr ; -reg [7: 0] wr_data ; -//三态门 -assign sda_en = 1'b1;//主机控制从机 -assign sda_in = sda; -assign sda = (sda_en == 1'b1)? i2c_sda : 1'bz; -//i2c驱动时钟设计 -always @(posedge sys_clk or negedge sys_rst_n) begin - if(!sys_rst_n)begin - cnt_clk <= 5'd0; - end - else if(cnt_clk == I2C_CLK_DIV)begin - cnt_clk <= 5'd0; - end - else begin - cnt_clk <= cnt_clk + 1; - end -end - -always @(posedge sys_clk or negedge sys_rst_n) begin - if(!sys_rst_n)begin - i2c_clk <= 1'b1; - end - else if(cnt_clk == I2C_CLK_DIV)begin - i2c_clk <= ~i2c_clk; - end - else begin - i2c_clk <= i2c_clk; - end -end -///////// -//状态机，第一段 -always @(posedge sys_clk or negedge sys_rst_n) begin - if(!sys_rst_n)begin - state_c <= IDLE; - end - else begin - state_c <= state_n; - end -end -//状态机第二段 -always @(*)begin - case(state_c) - IDLE: if(skip_en_1 == 1'b1)begin - state_n = START; - end - else begin - state_n = IDLE; - end - START: if(skip_en_1 == 1'b1)begin - state_n = SLAVE_ADDR; - end - else begin - state_n = START; - end - SLAVE_ADDR: if(skip_en_1 == 1'b1)begin - state_n = WAIT; - end - else begin - state_n = SLAVE_ADDR; - end - WAIT: if(skip_en_1 == 1'b1)begin - state_n = STOP; - end - else begin - state_n = WAIT; - end - STOP: if(skip_en_1 == 1'b1)begin - state_n = IDLE; - end - else begin - state_n = STOP; - end - default: begin - state_n = IDLE; - end - endcase -end -//状态机第三段 -always @(posedge i2c_clk or negedge sys_rst_n)begin - if(!sys_rst_n)begin - cnt_wait <= 10'd0; - skip_en_1 <= 1'b0; - step <= 3'd0; - cnt_i2c_clk <= 2'd0; - cnt_bit <= 3'd0; - i2c_end <= 1'b0; - end - else begin - case(state_c) - IDLE: begin - if(cnt_wait == MAX - 1)begin - cnt_wait <= 10'd0; - end - else begin - cnt_wait <= cnt_wait + 1; - end - if((cnt_wait == MAX - 2'd2) && (step == 3'd0))begin - skip_en_1 <= 1'b1; - end - else begin - skip_en_1 <= 1'b0; - end - end - START: begin - cnt_i2c_clk <= cnt_i2c_clk + 1'd1; - if((cnt_i2c_clk == 2'd2) && (step == 3'd0))begin - skip_en_1 <= 1'b1; - end - else begin - skip_en_1 <= 1'b0; - end - end - SLAVE_ADDR: begin - cnt_i2c_clk <= cnt_i2c_clk + 1'd1; - if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd0))begin - skip_en_1 <= 1'b1; - end - else begin - skip_en_1 <= 1'b0; - end - if((cnt_bit == 3'd7) && (cnt_i2c_clk == 2'd3))begin - cnt_bit <= 3'd0; - end - else if(cnt_i2c_clk == 2'd3)begin - cnt_bit <= cnt_bit + 1'd1; - end - else begin - cnt_bit <= cnt_bit; - end - end - WAIT: begin - if(cnt_wait == MAX - 1'd1)begin - cnt_wait = 10'd0; - end - else begin - cnt_wait <= cnt_wait + 1'd1; - end - if((cnt_wait == MAX - 2'd2) && (step == 3'd0))begin - skip_en_1 <= 1'b1; - end - else begin - skip_en_1 <= 1'b0; - end - end - STOP: begin - cnt_i2c_clk <= cnt_i2c_clk + 1'd1; - if((cnt_i2c_clk == 2'd2) && (step == 3'd0))begin - skip_en_1 <= 1'b1; - end - else begin - skip_en_1 <= 1'b0; - end - if(cnt_i2c_clk == 2'd2)begin - i2c_end <= 1'b1; - end - else begin - i2c_end <= 1'b0; - end - if(i2c_end == 1'b1)begin - step <= step + 1'd1; - end - else begin - step <= step; - end - end - default: begin - cnt_wait <= 10'd0; - skip_en_1 <= 1'b0; - step <= step; - cnt_i2c_clk <= 2'd0; - cnt_bit <= 3'd0; - i2c_end <= 1'b0; - end - endcase - end -end -//step -always @(*)begin - case(step) - 3'd0: begin - slave_addr = {SLAVE_ID, 1'b0}; - device_addr = 8'h0; - wr_data = 8'h0; - end - default:begin - slave_addr = 8'h0; - device_addr = 8'h0; - wr_data = 8'h0; - end - endcase -end -//i2c_scl -always @(*)begin - case(state_c) - IDLE: i2c_scl = 1'b1; - START: i2c_scl = (cnt_i2c_clk >= 2'd2) ? 1'b1 : 1'b0; - SLAVE_ADDR: i2c_scl = ((cnt_i2c_clk == 2'd1) || (cnt_i2c_clk == 2'd2)) ? 1'b1 : 1'b0; - WAIT: i2c_scl = 1'b0; - STOP: i2c_scl = (cnt_i2c_clk >= 2'd1) ? 1'b1 : 1'b0; - endcase -end -//i2c_sda -always @(*)begin - case(state_c) - IDLE: i2c_sda = 1'b1; - START: i2c_sda = (cnt_i2c_clk >= 2'd1) ? 1'b0 : 1'b1; - SLAVE_ADDR: i2c_sda = slave_addr[7 - cnt_bit]; - WAIT: i2c_sda = 1'b0; - STOP: i2c_sda = (cnt_i2c_clk >= 2'd2) ? 1'b1 : 1'b0; - default: i2c_sda = 1'b1; - endcase -end -assign scl = i2c_scl; +module i2c_ctrl( + input wire sys_clk , + input wire sys_rst_n , + + output wire scl , + inout wire sda + +); +parameter I2C_CLK_DIV = 5'd24, + MAX = 10'd1000, + SLAVE_ID = 7'h73; +//状态机参数定义 +parameter IDLE = 3'd0, + START = 3'd1, + SLAVE_ADDR= 3'd2, + WAIT = 3'd3, + STOP = 3'd4; +reg [2: 0] state_c; +reg [2: 0] state_n; +//// + +//i2c时钟计数器 +reg [4: 0] cnt_clk; +reg i2c_clk; +///// + +//中间信号定义 +reg [9: 0] cnt_wait ;//1000us +reg skip_en_1 ;//跳转信号 +reg [2: 0] step ;//步骤 +reg [1: 0] cnt_i2c_clk ;// +reg [2: 0] cnt_bit ;//bit计数器 +reg i2c_end ;//i2c结束信号 +wire sda_en ; +wire sda_in ; +reg i2c_sda ; +reg i2c_scl ; +reg [7: 0] slave_addr ; +reg [7: 0] device_addr ; +reg [7: 0] wr_data ; +//三态门 +assign sda_en = 1'b1;//主机控制从机 +assign sda_in = sda; +assign sda = (sda_en == 1'b1)? i2c_sda : 1'bz; +//i2c驱动时钟设计 +always @(posedge sys_clk or negedge sys_rst_n) begin + if(!sys_rst_n)begin + cnt_clk <= 5'd0; + end + else if(cnt_clk == I2C_CLK_DIV)begin + cnt_clk <= 5'd0; + end + else begin + cnt_clk <= cnt_clk + 1; + end +end + +always @(posedge sys_clk or negedge sys_rst_n) begin + if(!sys_rst_n)begin + i2c_clk <= 1'b1; + end + else if(cnt_clk == I2C_CLK_DIV)begin + i2c_clk <= ~i2c_clk; + end + else begin + i2c_clk <= i2c_clk; + end +end +///////// +//状态机，第一段 +always @(posedge sys_clk or negedge sys_rst_n) begin + if(!sys_rst_n)begin + state_c <= IDLE; + end + else begin + state_c <= state_n; + end +end +//状态机第二段 +always @(*)begin + case(state_c) + IDLE: if(skip_en_1 == 1'b1)begin + state_n = START; + end + else begin + state_n = IDLE; + end + START: if(skip_en_1 == 1'b1)begin + state_n = SLAVE_ADDR; + end + else begin + state_n = START; + end + SLAVE_ADDR: if(skip_en_1 == 1'b1)begin + state_n = WAIT; + end + else begin + state_n = SLAVE_ADDR; + end + WAIT: if(skip_en_1 == 1'b1)begin + state_n = STOP; + end + else begin + state_n = WAIT; + end + STOP: if(skip_en_1 == 1'b1)begin + state_n = IDLE; + end + else begin + state_n = STOP; + end + default: begin + state_n = IDLE; + end + endcase +end +//状态机第三段 +always @(posedge i2c_clk or negedge sys_rst_n)begin + if(!sys_rst_n)begin + cnt_wait <= 10'd0; + skip_en_1 <= 1'b0; + step <= 3'd0; + cnt_i2c_clk <= 2'd0; + cnt_bit <= 3'd0; + i2c_end <= 1'b0; + end + else begin + case(state_c) + IDLE: begin + if(cnt_wait == MAX - 1)begin + cnt_wait <= 10'd0; + end + else begin + cnt_wait <= cnt_wait + 1; + end + if((cnt_wait == MAX - 2'd2) && (step == 3'd0))begin + skip_en_1 <= 1'b1; + end + else begin + skip_en_1 <= 1'b0; + end + end + START: begin + cnt_i2c_clk <= cnt_i2c_clk + 1'd1; + if((cnt_i2c_clk == 2'd2) && (step == 3'd0))begin + skip_en_1 <= 1'b1; + end + else begin + skip_en_1 <= 1'b0; + end + end + SLAVE_ADDR: begin + cnt_i2c_clk <= cnt_i2c_clk + 1'd1; + if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd0))begin + skip_en_1 <= 1'b1; + end + else begin + skip_en_1 <= 1'b0; + end + if((cnt_bit == 3'd7) && (cnt_i2c_clk == 2'd3))begin + cnt_bit <= 3'd0; + end + else if(cnt_i2c_clk == 2'd3)begin + cnt_bit <= cnt_bit + 1'd1; + end + else begin + cnt_bit <= cnt_bit; + end + end + WAIT: begin + if(cnt_wait == MAX - 1'd1)begin + cnt_wait = 10'd0; + end + else begin + cnt_wait <= cnt_wait + 1'd1; + end + if((cnt_wait == MAX - 2'd2) && (step == 3'd0))begin + skip_en_1 <= 1'b1; + end + else begin + skip_en_1 <= 1'b0; + end + end + STOP: begin + cnt_i2c_clk <= cnt_i2c_clk + 1'd1; + if((cnt_i2c_clk == 2'd2) && (step == 3'd0))begin + skip_en_1 <= 1'b1; + end + else begin + skip_en_1 <= 1'b0; + end + if(cnt_i2c_clk == 2'd2)begin + i2c_end <= 1'b1; + end + else begin + i2c_end <= 1'b0; + end + if(i2c_end == 1'b1)begin + step <= step + 1'd1; + end + else begin + step <= step; + end + end + default: begin + cnt_wait <= 10'd0; + skip_en_1 <= 1'b0; + step <= step; + cnt_i2c_clk <= 2'd0; + cnt_bit <= 3'd0; + i2c_end <= 1'b0; + end + endcase + end +end +//step +always @(*)begin + case(step) + 3'd0: begin + slave_addr = {SLAVE_ID, 1'b0}; + device_addr = 8'h0; + wr_data = 8'h0; + end + default:begin + slave_addr = 8'h0; + device_addr = 8'h0; + wr_data = 8'h0; + end + endcase +end +//i2c_scl +always @(*)begin + case(state_c) + IDLE: i2c_scl = 1'b1; + START: i2c_scl = (cnt_i2c_clk >= 2'd2) ? 1'b1 : 1'b0; + SLAVE_ADDR: i2c_scl = ((cnt_i2c_clk == 2'd1) || (cnt_i2c_clk == 2'd2)) ? 1'b1 : 1'b0; + WAIT: i2c_scl = 1'b0; + STOP: i2c_scl = (cnt_i2c_clk >= 2'd1) ? 1'b1 : 1'b0; + endcase +end +//i2c_sda +always @(*)begin + case(state_c) + IDLE: i2c_sda = 1'b1; + START: i2c_sda = (cnt_i2c_clk >= 2'd1) ? 1'b0 : 1'b1; + SLAVE_ADDR: i2c_sda = slave_addr[7 - cnt_bit]; + WAIT: i2c_sda = 1'b0; + STOP: i2c_sda = (cnt_i2c_clk >= 2'd2) ? 1'b1 : 1'b0; + default: i2c_sda = 1'b1; + endcase +end +assign scl = i2c_scl; endmodule \ No newline at end of file diff --git a/rtl/led_ctrl.v b/hardware/rtl/led_ctrl.v similarity index 93% rename from rtl/led_ctrl.v rename to hardware/rtl/led_ctrl.v index 4959509..4acc81d 100644 --- a/rtl/led_ctrl.v +++ b/hardware/rtl/led_ctrl.v @@ -1,19 +1,19 @@ -module led_ctrl( - input wire sys_clk , - input wire sys_rst_n , - input wire [7: 0] po_data , - - output reg [3: 0] led -); -wire [3: 0] data; -assign data = po_data[3: 0]; -always @(posedge sys_clk or negedge sys_rst_n)begin - if(!sys_rst_n)begin - led <= 4'b0000; - end - else begin - led <= data; - end -end - +module led_ctrl( + input wire sys_clk , + input wire sys_rst_n , + input wire [7: 0] po_data , + + output reg [3: 0] led +); +wire [3: 0] data; +assign data = po_data[3: 0]; +always @(posedge sys_clk or negedge sys_rst_n)begin + if(!sys_rst_n)begin + led <= 4'b0000; + end + else begin + led <= data; + end +end + endmodule \ No newline at end of file diff --git a/rtl/paj7620_cfg.v b/hardware/rtl/paj7620_cfg.v similarity index 97% rename from rtl/paj7620_cfg.v rename to hardware/rtl/paj7620_cfg.v index 2bb55bc..5271933 100644 --- a/rtl/paj7620_cfg.v +++ b/hardware/rtl/paj7620_cfg.v @@ -1,86 +1,86 @@ -module paj7620_cfg( - input wire i2c_clk , - input wire sys_rst_n , - input wire cfg_start , - input wire [2: 0] step , - - output reg [5: 0] cfg_num , - output wire [15: 0] cfg_data , - output reg i2c_start -); -wire [15: 0] cfg_data_reg[50: 0]; -always @(posedge i2c_clk or negedge sys_rst_n)begin - if(!sys_rst_n)begin - cfg_num <= 6'd0; - end - else if((cfg_start == 1'b1) && (step == 3'd4))begin - cfg_num <= cfg_num + 1'd1; - end - else begin - cfg_num <= cfg_num; - end -end -always @(posedge i2c_clk or negedge sys_rst_n)begin - if(!sys_rst_n)begin - i2c_start <= 1'b0; - end - else if((cfg_data == 1'b1) && (step == 3'd4))begin - i2c_start <= 1'b1; - end - else begin - i2c_start <= 1'b0; - end -end -assign cfg_data = (step == 3'd4) ? cfg_data_reg[cfg_num - 1]:16'h0; -assign cfg_data_reg[00] = {8'hEF,8'h00}; -assign cfg_data_reg[01] = {8'h37,8'h07}; -assign cfg_data_reg[02] = {8'h38,8'h17}; -assign cfg_data_reg[03] = {8'h39,8'h06}; -assign cfg_data_reg[04] = {8'h42,8'h01}; -assign cfg_data_reg[05] = {8'h46,8'h2D}; -assign cfg_data_reg[06] = {8'h47,8'h0F}; -assign cfg_data_reg[07] = {8'h48,8'h3C}; -assign cfg_data_reg[08] = {8'h49,8'h00}; -assign cfg_data_reg[09] = {8'h4A,8'h1E}; -assign cfg_data_reg[10] = {8'h4C,8'h20}; -assign cfg_data_reg[11] = {8'h51,8'h10}; -assign cfg_data_reg[12] = {8'h5E,8'h10}; -assign cfg_data_reg[13] = {8'h60,8'h27}; -assign cfg_data_reg[14] = {8'h80,8'h42}; -assign cfg_data_reg[15] = {8'h81,8'h44}; -assign cfg_data_reg[16] = {8'h82,8'h04}; -assign cfg_data_reg[17] = {8'h8B,8'h01}; -assign cfg_data_reg[18] = {8'h90,8'h06}; -assign cfg_data_reg[19] = {8'h95,8'h0A}; -assign cfg_data_reg[20] = {8'h96,8'h0C}; -assign cfg_data_reg[21] = {8'h97,8'h05}; -assign cfg_data_reg[22] = {8'h9A,8'h14}; -assign cfg_data_reg[23] = {8'h9C,8'h3F}; -assign cfg_data_reg[24] = {8'hA5,8'h19}; -assign cfg_data_reg[25] = {8'hCC,8'h19}; -assign cfg_data_reg[26] = {8'hCD,8'h0B}; -assign cfg_data_reg[27] = {8'hCE,8'h13}; -assign cfg_data_reg[28] = {8'hCF,8'h64}; -assign cfg_data_reg[29] = {8'hD0,8'h21}; -assign cfg_data_reg[30] = {8'hEF,8'h01}; -assign cfg_data_reg[31] = {8'h02,8'h0F}; -assign cfg_data_reg[32] = {8'h03,8'h10}; -assign cfg_data_reg[33] = {8'h04,8'h02}; -assign cfg_data_reg[34] = {8'h25,8'h01}; -assign cfg_data_reg[35] = {8'h27,8'h39}; -assign cfg_data_reg[36] = {8'h28,8'h7F}; -assign cfg_data_reg[37] = {8'h29,8'h08}; -assign cfg_data_reg[38] = {8'h3E,8'hFF}; -assign cfg_data_reg[39] = {8'h5E,8'h3D}; -assign cfg_data_reg[40] = {8'h65,8'h96}; -assign cfg_data_reg[41] = {8'h67,8'h97}; -assign cfg_data_reg[42] = {8'h69,8'hCD}; -assign cfg_data_reg[43] = {8'h6A,8'h01}; -assign cfg_data_reg[44] = {8'h6D,8'h2C}; -assign cfg_data_reg[45] = {8'h6E,8'h01}; -assign cfg_data_reg[46] = {8'h72,8'h01}; -assign cfg_data_reg[47] = {8'h73,8'h35}; -assign cfg_data_reg[48] = {8'h74,8'h00}; -assign cfg_data_reg[49] = {8'h77,8'h01}; -assign cfg_data_reg[50] = {8'hEF,8'h00}; +module paj7620_cfg( + input wire i2c_clk , + input wire sys_rst_n , + input wire cfg_start , + input wire [2: 0] step , + + output reg [5: 0] cfg_num , + output wire [15: 0] cfg_data , + output reg i2c_start +); +wire [15: 0] cfg_data_reg[50: 0]; +always @(posedge i2c_clk or negedge sys_rst_n)begin + if(!sys_rst_n)begin + cfg_num <= 6'd0; + end + else if((cfg_start == 1'b1) && (step == 3'd4))begin + cfg_num <= cfg_num + 1'd1; + end + else begin + cfg_num <= cfg_num; + end +end +always @(posedge i2c_clk or negedge sys_rst_n)begin + if(!sys_rst_n)begin + i2c_start <= 1'b0; + end + else if((cfg_data == 1'b1) && (step == 3'd4))begin + i2c_start <= 1'b1; + end + else begin + i2c_start <= 1'b0; + end +end +assign cfg_data = (step == 3'd4) ? cfg_data_reg[cfg_num - 1]:16'h0; +assign cfg_data_reg[00] = {8'hEF,8'h00}; +assign cfg_data_reg[01] = {8'h37,8'h07}; +assign cfg_data_reg[02] = {8'h38,8'h17}; +assign cfg_data_reg[03] = {8'h39,8'h06}; +assign cfg_data_reg[04] = {8'h42,8'h01}; +assign cfg_data_reg[05] = {8'h46,8'h2D}; +assign cfg_data_reg[06] = {8'h47,8'h0F}; +assign cfg_data_reg[07] = {8'h48,8'h3C}; +assign cfg_data_reg[08] = {8'h49,8'h00}; +assign cfg_data_reg[09] = {8'h4A,8'h1E}; +assign cfg_data_reg[10] = {8'h4C,8'h20}; +assign cfg_data_reg[11] = {8'h51,8'h10}; +assign cfg_data_reg[12] = {8'h5E,8'h10}; +assign cfg_data_reg[13] = {8'h60,8'h27}; +assign cfg_data_reg[14] = {8'h80,8'h42}; +assign cfg_data_reg[15] = {8'h81,8'h44}; +assign cfg_data_reg[16] = {8'h82,8'h04}; +assign cfg_data_reg[17] = {8'h8B,8'h01}; +assign cfg_data_reg[18] = {8'h90,8'h06}; +assign cfg_data_reg[19] = {8'h95,8'h0A}; +assign cfg_data_reg[20] = {8'h96,8'h0C}; +assign cfg_data_reg[21] = {8'h97,8'h05}; +assign cfg_data_reg[22] = {8'h9A,8'h14}; +assign cfg_data_reg[23] = {8'h9C,8'h3F}; +assign cfg_data_reg[24] = {8'hA5,8'h19}; +assign cfg_data_reg[25] = {8'hCC,8'h19}; +assign cfg_data_reg[26] = {8'hCD,8'h0B}; +assign cfg_data_reg[27] = {8'hCE,8'h13}; +assign cfg_data_reg[28] = {8'hCF,8'h64}; +assign cfg_data_reg[29] = {8'hD0,8'h21}; +assign cfg_data_reg[30] = {8'hEF,8'h01}; +assign cfg_data_reg[31] = {8'h02,8'h0F}; +assign cfg_data_reg[32] = {8'h03,8'h10}; +assign cfg_data_reg[33] = {8'h04,8'h02}; +assign cfg_data_reg[34] = {8'h25,8'h01}; +assign cfg_data_reg[35] = {8'h27,8'h39}; +assign cfg_data_reg[36] = {8'h28,8'h7F}; +assign cfg_data_reg[37] = {8'h29,8'h08}; +assign cfg_data_reg[38] = {8'h3E,8'hFF}; +assign cfg_data_reg[39] = {8'h5E,8'h3D}; +assign cfg_data_reg[40] = {8'h65,8'h96}; +assign cfg_data_reg[41] = {8'h67,8'h97}; +assign cfg_data_reg[42] = {8'h69,8'hCD}; +assign cfg_data_reg[43] = {8'h6A,8'h01}; +assign cfg_data_reg[44] = {8'h6D,8'h2C}; +assign cfg_data_reg[45] = {8'h6E,8'h01}; +assign cfg_data_reg[46] = {8'h72,8'h01}; +assign cfg_data_reg[47] = {8'h73,8'h35}; +assign cfg_data_reg[48] = {8'h74,8'h00}; +assign cfg_data_reg[49] = {8'h77,8'h01}; +assign cfg_data_reg[50] = {8'hEF,8'h00}; endmodule \ No newline at end of file diff --git a/rtl/param.v b/hardware/rtl/param.v similarity index 100% rename from rtl/param.v rename to hardware/rtl/param.v diff --git a/rtl/uart_rx.v b/hardware/rtl/uart_rx.v similarity index 100% rename from rtl/uart_rx.v rename to hardware/rtl/uart_rx.v diff --git a/rtl/uart_top.v b/hardware/rtl/uart_top.v similarity index 100% rename from rtl/uart_top.v rename to hardware/rtl/uart_top.v diff --git a/rtl/uart_tx.v b/hardware/rtl/uart_tx.v similarity index 100% rename from rtl/uart_tx.v rename to hardware/rtl/uart_tx.v diff --git a/hardware/tcl/gesture_tiktok.tcl b/hardware/tcl/gesture_tiktok.tcl new file mode 100644 index 0000000..956bb98 --- /dev/null +++ b/hardware/tcl/gesture_tiktok.tcl @@ -0,0 +1,29 @@ +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. + +# Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# File: C:\Users\Stark-lin\Desktop\gesture_tiktok\hardware\tcl\gesture_tiktok.tcl +# Generated on: Tue May 21 08:18:12 2024 + +package require ::quartus::project + +set_location_assignment PIN_D8 -to sda +set_location_assignment PIN_E7 -to scl +set_location_assignment PIN_E1 -to sys_clk +set_location_assignment PIN_E15 -to sys_rst_n +set_location_assignment PIN_G1 -to tx +set_location_assignment PIN_G15 -to led[0] +set_location_assignment PIN_F16 -to led[1] +set_location_assignment PIN_F15 -to led[2] +set_location_assignment PIN_D16 -to led[3] diff --git a/software/main.go b/software/main.go index d434501..9c1aa79 100644 --- a/software/main.go +++ b/software/main.go @@ -3,6 +3,7 @@ package main import ( "fmt" "log" + "regexp" "time" "github.com/StackExchange/wmi" @@ -23,7 +24,9 @@ func check() string { panic(fmt.Sprintf("Failed to query WMI: %v", err)) } - return devices[0].Name[40:44] + re := regexp.MustCompile(`COM\d+`) + dev := re.FindString(devices[0].Name) + return dev //获取串口名字 } func main() { // 串口配置 @@ -57,6 +60,8 @@ func main() { } else if buffer[0] == 0x02 { robotgo.KeyPress("down") + } else if buffer[0] == 0x04 { + robotgo.KeyPress("z") } else if buffer[0] == 0x10 { robotgo.KeyPress("f") } else { diff --git a/software/tiktok.exe b/software/tiktok.exe index 6956e19..72626e6 100644 Binary files a/software/tiktok.exe and b/software/tiktok.exe differ diff --git a/tools/sscom5.13.1.exe b/tools/sscom5.13.1.exe new file mode 100644 index 0000000..1fe2df0 Binary files /dev/null and b/tools/sscom5.13.1.exe differ diff --git a/tools/sscom51.ini b/tools/sscom51.ini new file mode 100644 index 0000000..a73fab3 --- /dev/null +++ b/tools/sscom51.ini @@ -0,0 +1,383 @@ +;ɾļԻָĬֵ +;SSCOMñļ,ڳúõĴڲַݶԶ,òҪⲿ༭Ķļ! +;ļ޸ĺܴ,ɾļ,򽫻Զһµiniļ. +;׵İǷֺעͷ +;ÿжԻس + +;"="HʾǸHEXݴ +;"="AʾǸASCַ +;Nxʾڼַ(1