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64 lines
1.6 KiB
Verilog
64 lines
1.6 KiB
Verilog
module ges_recognize(
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input wire sys_clk ,
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input wire sys_rst_n ,
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output wire scl ,
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inout wire sda ,
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output wire [3: 0] led ,
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output wire tx
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);
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wire [2: 0] step ;
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wire [5: 0] cfg_num ;
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wire [15: 0] cfg_data ;
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wire cfg_start ;
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wire i2c_clk ;
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wire i2c_start ;
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wire [7: 0] po_data ;
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wire tx_vld ;
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reg send_flag ;
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wire rx_vld ;
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assign rx_vld = po_data != 8'h00;
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paj7620_cfg paj7620_cfg_inst(
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.i2c_clk (i2c_clk ),
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.sys_rst_n (sys_rst_n ),
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.cfg_start (cfg_start ),
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.step (step ),
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.cfg_num (cfg_num ),
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.cfg_data (cfg_data ),
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.i2c_start (i2c_start )
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);
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i2c_ctrl i2c_ctrl_inst(
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.sys_clk (sys_clk ),
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.sys_rst_n (sys_rst_n ),
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.i2c_start (i2c_start ),
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.cfg_num (cfg_num ),
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.cfg_data (cfg_data ),
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.cfg_start (cfg_start ),
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.step (step ),
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.i2c_clk (i2c_clk ),
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.scl (scl ),
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.sda (sda ),
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.po_data (po_data )
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);
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uart_tx uart_tx_inst(
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.sys_clk (sys_clk),
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.sys_rst_n (sys_rst_n),
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.tx_din (po_data),//并行输入，接受模块传入
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.rx_vld (rx_vld),//接受模块，串转并有效信号
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.tx_vld (tx_vld),
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.tx_dout (tx)//串行输出
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);
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led_ctrl led_ctrl_inst(
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.sys_clk (sys_clk ),
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.sys_rst_n (sys_rst_n ),
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.po_data (po_data ),
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.led (led )
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);
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endmodule |