module led_ctrl(
    input   wire        sys_clk     ,
    input   wire        sys_rst_n   ,
    input   wire [3: 0] ges_data     ,

    output  reg  [3: 0] led
);
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        led <= 4'b0000;
    end 
    else begin
        led <= ges_data;
    end
end 

endmodule