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72 lines
1.7 KiB
Verilog
72 lines
1.7 KiB
Verilog
module ges_ws2812(
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input wire sys_clk ,
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input wire sys_rst_n ,
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output wire scl ,
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inout wire sda ,
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output wire [3: 0] led ,
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output wire dout
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);
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wire [2: 0] step ;
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wire [5: 0] cfg_num ;
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wire [15: 0] cfg_data ;
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wire cfg_start ;
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wire i2c_clk ;
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wire i2c_start ;
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wire [7: 0] po_data ;
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wire [3: 0] ges_data ;
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wire bit ;
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wire [4: 0] cnt_bit ;
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wire [6: 0] cnt_pixel ;
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assign ges_data = po_data[3: 0];
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paj7620_cfg paj7620_cfg_inst(
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.i2c_clk (i2c_clk ),
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.sys_rst_n (sys_rst_n ),
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.cfg_start (cfg_start ),
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.step (step ),
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.cfg_num (cfg_num ),
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.cfg_data (cfg_data ),
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.i2c_start (i2c_start )
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);
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i2c_ctrl i2c_ctrl_inst(
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.sys_clk (sys_clk ),
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.sys_rst_n (sys_rst_n ),
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.i2c_start (i2c_start ),
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.cfg_num (cfg_num ),
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.cfg_data (cfg_data ),
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.cfg_start (cfg_start ),
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.step (step ),
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.i2c_clk (i2c_clk ),
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.scl (scl ),
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.sda (sda ),
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.po_data (po_data )
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);
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led_ctrl led_ctrl_inst(
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.sys_clk (sys_clk ),
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.sys_rst_n (sys_rst_n ),
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.ges_data (ges_data ),
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.led (led )
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);
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ws2812_ctrl ws2812_ctrl_inst(
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.sys_clk (sys_clk ),
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.sys_rst_n (sys_rst_n ),
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.bit (bit ),//01数据
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.cnt_bit (cnt_bit ),
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.cnt_pixel (cnt_pixel ),
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.dout (dout )
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);
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data_cfg data_cfg_inst(
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.cnt_bit (cnt_bit ),
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.cnt_pixel (cnt_pixel ),
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.ges_data (ges_data ),
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.bit (bit )
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);
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endmodule |