half_adder/rtl/top.v

module top(
    input   wire            sys_clk     ,
    input   wire            sys_rst_n   ,
    input   wire [1: 0]     key_in      ,

    output  wire            sum         ,
    output  wire            cout
);

wire [1: 0] key_out;
reg  flag_key0;
reg  flag_key1;

half_adder  half_adder_inst(
.cin        ({flag_key0, flag_key1}),//in1, in2
    
.sum        (sum),
.cout       (cout) 
);




always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        flag_key0 <= 1'b0;
        flag_key1 <= 1'b0;
    end 
    else if(key_out[0])begin
        flag_key0 <= ~flag_key0;
        flag_key1 <= flag_key1;
    end  
    else if(key_out[1])begin
        flag_key0 <= flag_key0;
        flag_key1 <= ~flag_key1;
    end   
    else begin
        flag_key0 <= flag_key0;
        flag_key1 <= flag_key1;
    end 
end 
key_filter #(.KEY_W(2), .DELAY(1000_000)) key_filter_inst(//2
.sys_clk        (sys_clk),
.sys_rst_n      (sys_rst_n),
.key_in         (key_in),

.key_out        (key_out)
);	
endmodule