module key_ctrl(
    input   wire  sys_clk   ,
    input   wire  sys_rst_n ,
    input   wire  key       ,

    output  reg   led
);
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        led <= 1'b0;
    end 
    else if(key == 1'b1)begin
        led <= ~led;
    end 
    else begin
        led <= led;
    end 
end 
endmodule