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module key_ctrl(
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input wire sys_clk ,
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input wire sys_rst_n ,
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input wire key ,
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output reg led
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);
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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led <= 1'b0;
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end
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else if(key == 1'b1)begin
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led <= ~led;
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end
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else begin
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led <= led;
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end
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end
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endmodule |