You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
36 lines
783 B
Verilog
36 lines
783 B
Verilog
module key_debounce(
|
|
input wire sys_clk ,
|
|
input wire sys_rst_n ,
|
|
input wire key_in ,
|
|
|
|
output reg key_out
|
|
);
|
|
parameter MAX = 20'd999_999;
|
|
reg [19: 0] cnt_20ms;
|
|
always @(posedge sys_clk or negedge sys_rst_n) begin
|
|
if(!sys_rst_n)begin
|
|
cnt_20ms <= 20'd0;
|
|
end
|
|
else if(key_in == 1'b1)begin
|
|
cnt_20ms <= 20'd0;
|
|
end
|
|
else if((cnt_20ms == MAX) && (key_in == 1'b0))begin
|
|
cnt_20ms <= cnt_20ms;
|
|
end
|
|
else begin
|
|
cnt_20ms <= cnt_20ms + 1'd1;
|
|
end
|
|
end
|
|
|
|
always @(posedge sys_clk or negedge sys_rst_n)begin
|
|
if(!sys_rst_n)begin
|
|
key_out <= 1'b0;
|
|
end
|
|
else if(cnt_20ms == MAX - 1'd1)begin
|
|
key_out <= 1'b1;
|
|
end
|
|
else begin
|
|
key_out <= 1'b0;
|
|
end
|
|
end
|
|
endmodule |