module pll_ctrl(
    input   wire        sys_clk     ,
    input   wire        sys_rst_n   ,

    output  wire [3: 0] led
);
parameter  MAX = 26'd50_000_000;
wire clk_25;//40ns
wire clk_50;//20ns
wire clk_100;//10ns
wire clk_200;//5ns
reg [25: 0] cnt_25;
wire        add_cnt_25;
wire        end_cnt_25;
reg         flag_25;
reg [25: 0] cnt_50;
wire        add_cnt_50;
wire        end_cnt_50;
reg         flag_50;
reg [25: 0] cnt_100;
wire        add_cnt_100;
wire        end_cnt_100;
reg         flag_100;
reg [25: 0] cnt_200;
wire        add_cnt_200;
wire        end_cnt_200;
reg         flag_200;
always @(posedge clk_25 or negedge sys_rst_n) begin
    if(!sys_rst_n)begin
        cnt_25 <= 26'd0;
    end 
    else if(add_cnt_25)begin
        if(end_cnt_25)begin
            cnt_25 <= 26'd0;
        end 
        else begin
            cnt_25 <= cnt_25 + 1'd1;
        end 
    end 
    else begin
        cnt_25 <= cnt_25;
    end 
end
assign add_cnt_25 = 1'b1;
assign end_cnt_25 = add_cnt_25 && cnt_25 == MAX - 1'd1;

always @(posedge clk_50 or negedge sys_rst_n) begin
    if(!sys_rst_n)begin
        cnt_50 <= 26'd0;
    end 
    else if(add_cnt_50)begin
        if(end_cnt_50)begin
            cnt_50 <= 26'd0;
        end 
        else begin
            cnt_50 <= cnt_50 + 1'd1;
        end 
    end 
    else begin
        cnt_50 <= cnt_50;
    end 
end
assign add_cnt_50 = 1'b1;
assign end_cnt_50 = add_cnt_50 && cnt_50 == MAX - 1'd1;

always @(posedge clk_100 or negedge sys_rst_n) begin
    if(!sys_rst_n)begin
        cnt_100 <= 26'd0;
    end 
    else if(add_cnt_100)begin
        if(end_cnt_100)begin
            cnt_100 <= 26'd0;
        end 
        else begin
            cnt_100 <= cnt_100 + 1'd1;
        end 
    end 
    else begin
        cnt_100 <= cnt_100;
    end 
end
assign add_cnt_100 = 1'b1;
assign end_cnt_100 = add_cnt_100 && cnt_100 == MAX - 1'd1;

always @(posedge clk_200 or negedge sys_rst_n) begin
    if(!sys_rst_n)begin
        cnt_200 <= 26'd0;
    end 
    else if(add_cnt_200)begin
        if(end_cnt_200)begin
            cnt_200 <= 26'd0;
        end 
        else begin
            cnt_200 <= cnt_200 + 1'd1;
        end 
    end 
    else begin
        cnt_200 <= cnt_200;
    end 
end
assign add_cnt_200 = 1'b1;
assign end_cnt_200 = add_cnt_200 && cnt_200 == MAX - 1'd1;
always @(posedge clk_25 or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        flag_25 <= 1'b0;
    end 
    else if(end_cnt_25)begin
        flag_25 <= ~flag_25;
    end 
    else begin
        flag_25 <= flag_25;
    end 
end 

always @(posedge clk_50 or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        flag_50 <= 1'b0;
    end 
    else if(end_cnt_50)begin
        flag_50 <= ~flag_50;
    end 
    else begin
        flag_50 <= flag_50;
    end 
end 

always @(posedge clk_100 or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        flag_100 <= 1'b0;
    end 
    else if(end_cnt_100)begin
        flag_100 <= ~flag_100;
    end 
    else begin
        flag_100 <= flag_100;
    end 
end 

always @(posedge clk_200 or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        flag_200 <= 1'b0;
    end 
    else if(end_cnt_200)begin
        flag_200 <= ~flag_200;
    end 
    else begin
        flag_200 <= flag_200;
    end 
end 

assign led = {flag_25, flag_50, flag_100, flag_200};
pll_ip	pll_ip_inst (
	.areset ( ~sys_rst_n ),
	.inclk0 ( sys_clk ),
	.c0 ( clk_25 ),
	.c1 ( clk_50 ),
	.c2 ( clk_100 ),
	.c3 ( clk_200 )
	);







endmodule