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167 lines
3.4 KiB
Verilog
167 lines
3.4 KiB
Verilog
module pll_ctrl(
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input wire sys_clk ,
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input wire sys_rst_n ,
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output wire [3: 0] led
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);
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parameter MAX = 26'd50_000_000;
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wire clk_25;//40ns
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wire clk_50;//20ns
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wire clk_100;//10ns
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wire clk_200;//5ns
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reg [25: 0] cnt_25;
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wire add_cnt_25;
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wire end_cnt_25;
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reg flag_25;
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reg [25: 0] cnt_50;
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wire add_cnt_50;
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wire end_cnt_50;
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reg flag_50;
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reg [25: 0] cnt_100;
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wire add_cnt_100;
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wire end_cnt_100;
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reg flag_100;
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reg [25: 0] cnt_200;
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wire add_cnt_200;
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wire end_cnt_200;
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reg flag_200;
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always @(posedge clk_25 or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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cnt_25 <= 26'd0;
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end
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else if(add_cnt_25)begin
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if(end_cnt_25)begin
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cnt_25 <= 26'd0;
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end
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else begin
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cnt_25 <= cnt_25 + 1'd1;
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end
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end
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else begin
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cnt_25 <= cnt_25;
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end
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end
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assign add_cnt_25 = 1'b1;
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assign end_cnt_25 = add_cnt_25 && cnt_25 == MAX - 1'd1;
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always @(posedge clk_50 or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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cnt_50 <= 26'd0;
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end
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else if(add_cnt_50)begin
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if(end_cnt_50)begin
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cnt_50 <= 26'd0;
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end
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else begin
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cnt_50 <= cnt_50 + 1'd1;
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end
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end
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else begin
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cnt_50 <= cnt_50;
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end
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end
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assign add_cnt_50 = 1'b1;
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assign end_cnt_50 = add_cnt_50 && cnt_50 == MAX - 1'd1;
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always @(posedge clk_100 or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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cnt_100 <= 26'd0;
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end
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else if(add_cnt_100)begin
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if(end_cnt_100)begin
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cnt_100 <= 26'd0;
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end
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else begin
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cnt_100 <= cnt_100 + 1'd1;
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end
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end
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else begin
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cnt_100 <= cnt_100;
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end
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end
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assign add_cnt_100 = 1'b1;
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assign end_cnt_100 = add_cnt_100 && cnt_100 == MAX - 1'd1;
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always @(posedge clk_200 or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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cnt_200 <= 26'd0;
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end
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else if(add_cnt_200)begin
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if(end_cnt_200)begin
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cnt_200 <= 26'd0;
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end
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else begin
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cnt_200 <= cnt_200 + 1'd1;
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end
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end
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else begin
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cnt_200 <= cnt_200;
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end
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end
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assign add_cnt_200 = 1'b1;
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assign end_cnt_200 = add_cnt_200 && cnt_200 == MAX - 1'd1;
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always @(posedge clk_25 or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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flag_25 <= 1'b0;
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end
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else if(end_cnt_25)begin
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flag_25 <= ~flag_25;
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end
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else begin
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flag_25 <= flag_25;
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end
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end
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always @(posedge clk_50 or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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flag_50 <= 1'b0;
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end
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else if(end_cnt_50)begin
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flag_50 <= ~flag_50;
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end
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else begin
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flag_50 <= flag_50;
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end
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end
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always @(posedge clk_100 or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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flag_100 <= 1'b0;
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end
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else if(end_cnt_100)begin
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flag_100 <= ~flag_100;
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end
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else begin
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flag_100 <= flag_100;
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end
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end
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always @(posedge clk_200 or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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flag_200 <= 1'b0;
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end
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else if(end_cnt_200)begin
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flag_200 <= ~flag_200;
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end
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else begin
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flag_200 <= flag_200;
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end
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end
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assign led = {flag_25, flag_50, flag_100, flag_200};
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pll_ip pll_ip_inst (
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.areset ( ~sys_rst_n ),
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.inclk0 ( sys_clk ),
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.c0 ( clk_25 ),
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.c1 ( clk_50 ),
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.c2 ( clk_100 ),
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.c3 ( clk_200 )
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);
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endmodule |