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19 lines
369 B
Coq

7 months ago
module pwm_beep(
input wire sys_clk ,
input wire sys_rst_n ,
input wire pwm ,
output reg beep
);
always @(posedge sys_clk or negedge sys_rst_n)begin
if(!sys_rst_n)begin
beep <= 1'b1;
end
else if(pwm)begin
beep <= 1'b0;
end
else begin
beep <= 1'b1;
end
end
endmodule