finish

readme.md

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+## FPGA pwm 音乐
+### pwm脉宽调制
+### 蜂鸣器控制

rtl/freq_select.v

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+module freq_select(
+    input   wire sys_clk    ,
+    input   wire sys_rst_n  ,
+
+    output  wire pwm
+);
+parameter MAX   = 24'd15_000_000;//300ms最大数
+parameter NOTE  = 6'd34;//音符个数
+parameter DO = 16'd47750,//1
+          RE = 16'd42550,//2
+          MI = 16'd37900,//3
+          FA = 16'd37550,//4
+          SO = 16'd31850,//5
+          LA = 16'd28400,//6
+          XI = 16'd25400;//7
+
+          
+reg [23: 0] cnt_300 ;
+reg [5: 0]  cnt_note;
+reg [15: 0] cnt_freq;
+wire [15: 0] duty   ;//占空比
+reg [15: 0] X;
+//300ms计数器设计
+always @(posedge sys_clk or negedge sys_rst_n) begin
+    if(!sys_rst_n)begin
+        cnt_300 <= 24'd0;
+    end 
+    else if(cnt_300 == MAX - 1'd1)begin
+        cnt_300 <= 24'd0;
+    end 
+    else begin
+        cnt_300 <= cnt_300 + 1'd1;
+    end 
+end
+
+//34个音符计数器设计
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        cnt_note <= 6'd0;
+    end 
+    else if((cnt_note == NOTE - 1'd1) && (cnt_300 == MAX - 1'd1))begin
+        cnt_note <= 6'd0;
+    end 
+    else if(cnt_300 == MAX - 1'd1)begin
+        cnt_note <= cnt_note + 1'd1;
+    end 
+    else begin
+        cnt_note <= cnt_note;
+    end 
+end 
+
+//每个音符频率计数器
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        cnt_freq <= 16'd0;
+    end 
+    else if(cnt_freq == X - 1)begin
+        cnt_freq <= 16'd0;
+    end 
+    else begin
+        cnt_freq <= cnt_freq + 1'd1;
+    end 
+end 
+
+//查找表
+always @(*)begin
+    case(cnt_note)
+        6'd0   :  X = DO;//1
+        6'd1   :  X = RE;//2
+        6'd2   :  X = MI;//3
+        6'd3   :  X = DO;//1
+        6'd4   :  X = DO;//1
+        6'd5   :  X = RE;//2
+        6'd6   :  X = MI;//3
+        6'd7   :  X = DO;//1
+        6'd8   :  X = MI;//3
+        6'd9   :  X = FA;//4
+        6'd10  :  X = SO;//5
+        6'd11  :  X = MI;//3
+        6'd12  :  X = FA;//4
+        6'd13  :  X = SO;//5
+        6'd14  :  X = SO;//5
+        6'd15  :  X = LA;//6
+        6'd16  :  X = SO;//5
+        6'd17  :  X = FA;//4
+        6'd18  :  X = MI;//3
+        6'd19  :  X = DO;//1
+        6'd20  :  X = SO;//5
+        6'd21  :  X = LA;//6
+        6'd22  :  X = SO;//5
+        6'd23  :  X = FA;//4
+        6'd24  :  X = MI;//3
+        6'd25  :  X = DO;//1
+        6'd26  :  X = RE;//2
+        6'd27  :  X = SO;//5
+        6'd28  :  X = DO;//1
+        6'd29  :  X = DO;//1
+        6'd30  :  X = RE;//2
+        6'd31  :  X = SO;//5
+        6'd32  :  X = DO;//1
+        6'd33  :  X = DO;//1
+        default:  X = DO;//1
+    endcase
+end 
+assign duty = X >> 1;//占空比是1/2
+assign pwm = (cnt_freq >= duty) ? 1'b0: 1'b1; 
+endmodule 

rtl/music_top.v

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+module music_top(
+    input   wire sys_clk    ,
+    input   wire sys_rst_n  ,
+
+    output  wire beep
+);
+wire pwm;
+
+freq_select freq_select_inst(
+.sys_clk        (sys_clk),
+.sys_rst_n      (sys_rst_n),
+    
+.pwm            (pwm)
+);
+
+pwm_beep    pwm_beep_inst(
+.sys_clk        (sys_clk),
+.sys_rst_n      (sys_rst_n),
+.pwm            (pwm),
+
+.beep           (beep)
+);
+// defparam freq_select_inst.MAX = 100;//100 * 34 * 20 = 68000ns
+// defparam freq_select_inst.DO = 80,
+        //  freq_select_inst.RE = 60,
+        //  freq_select_inst.MI = 50,
+        //  freq_select_inst.FA = 40,
+        //  freq_select_inst.SO = 30,
+        //  freq_select_inst.LA = 20,
+        //  freq_select_inst.XI = 10;
+
+endmodule

rtl/pwm_beep.v

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+module pwm_beep(
+    input   wire    sys_clk     ,
+    input   wire    sys_rst_n   ,
+    input   wire    pwm         ,
+
+    output  reg     beep
+);
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        beep <= 1'b1;
+    end 
+    else if(pwm)begin
+        beep <= 1'b0;
+    end
+    else begin
+        beep <= 1'b1;
+    end  
+end 
+endmodule 

tb/music_tb.v

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+`timescale 1ns/1ns
+module music_tb();
+parameter CYCLE = 20;//时钟周期
+reg sys_clk     ;
+reg sys_rst_n   ;
+wire beep       ;
+always #(CYCLE / 2) sys_clk = ~sys_clk;
+
+initial begin
+    sys_clk   = 1'b0;
+    sys_rst_n = 1'b0;
+    #(CYCLE);
+    sys_rst_n = 1'b1;
+    #(CYCLE * 100 * 34);
+    $stop;
+end
+music_top   music_top_inst(
+.sys_clk        (sys_clk),
+.sys_rst_n      (sys_rst_n),
+    
+.beep           (beep)
+);
+endmodule

tcl/pwm_music_10.tcl

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+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+
+# Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
+# File: D:\sdkj_projects\pwm_music_10\tcl\pwm_music_10.tcl
+# Generated on: Tue Jan 02 15:15:23 2024
+
+package require ::quartus::project
+
+set_location_assignment PIN_J1 -to beep
+set_location_assignment PIN_E1 -to sys_clk
+set_location_assignment PIN_E15 -to sys_rst_n