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107 lines
2.6 KiB
Verilog
107 lines
2.6 KiB
Verilog
module freq_select(
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input wire sys_clk ,
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input wire sys_rst_n ,
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output wire pwm
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);
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parameter MAX = 24'd15_000_000;//300ms最大数
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parameter NOTE = 6'd34;//音符个数
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parameter DO = 16'd47750,//1
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RE = 16'd42550,//2
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MI = 16'd37900,//3
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FA = 16'd37550,//4
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SO = 16'd31850,//5
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LA = 16'd28400,//6
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XI = 16'd25400;//7
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reg [23: 0] cnt_300 ;
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reg [5: 0] cnt_note;
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reg [15: 0] cnt_freq;
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wire [15: 0] duty ;//占空比
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reg [15: 0] X;
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//300ms计数器设计
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always @(posedge sys_clk or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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cnt_300 <= 24'd0;
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end
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else if(cnt_300 == MAX - 1'd1)begin
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cnt_300 <= 24'd0;
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end
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else begin
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cnt_300 <= cnt_300 + 1'd1;
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end
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end
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//34个音符计数器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_note <= 6'd0;
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end
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else if((cnt_note == NOTE - 1'd1) && (cnt_300 == MAX - 1'd1))begin
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cnt_note <= 6'd0;
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end
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else if(cnt_300 == MAX - 1'd1)begin
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cnt_note <= cnt_note + 1'd1;
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end
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else begin
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cnt_note <= cnt_note;
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end
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end
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//每个音符频率计数器
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_freq <= 16'd0;
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end
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else if(cnt_freq == X - 1)begin
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cnt_freq <= 16'd0;
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end
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else begin
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cnt_freq <= cnt_freq + 1'd1;
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end
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end
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//查找表
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always @(*)begin
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case(cnt_note)
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6'd0 : X = DO;//1
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6'd1 : X = RE;//2
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6'd2 : X = MI;//3
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6'd3 : X = DO;//1
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6'd4 : X = DO;//1
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6'd5 : X = RE;//2
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6'd6 : X = MI;//3
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6'd7 : X = DO;//1
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6'd8 : X = MI;//3
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6'd9 : X = FA;//4
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6'd10 : X = SO;//5
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6'd11 : X = MI;//3
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6'd12 : X = FA;//4
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6'd13 : X = SO;//5
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6'd14 : X = SO;//5
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6'd15 : X = LA;//6
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6'd16 : X = SO;//5
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6'd17 : X = FA;//4
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6'd18 : X = MI;//3
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6'd19 : X = DO;//1
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6'd20 : X = SO;//5
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6'd21 : X = LA;//6
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6'd22 : X = SO;//5
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6'd23 : X = FA;//4
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6'd24 : X = MI;//3
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6'd25 : X = DO;//1
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6'd26 : X = RE;//2
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6'd27 : X = SO;//5
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6'd28 : X = DO;//1
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6'd29 : X = DO;//1
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6'd30 : X = RE;//2
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6'd31 : X = SO;//5
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6'd32 : X = DO;//1
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6'd33 : X = DO;//1
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default: X = DO;//1
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endcase
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end
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assign duty = X >> 1;//占空比是1/2
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assign pwm = (cnt_freq >= duty) ? 1'b0: 1'b1;
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endmodule
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