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32 lines
706 B
Verilog
32 lines
706 B
Verilog
module music_top(
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input wire sys_clk ,
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input wire sys_rst_n ,
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output wire beep
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);
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wire pwm;
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freq_select freq_select_inst(
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.sys_clk (sys_clk),
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.sys_rst_n (sys_rst_n),
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.pwm (pwm)
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);
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pwm_beep pwm_beep_inst(
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.sys_clk (sys_clk),
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.sys_rst_n (sys_rst_n),
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.pwm (pwm),
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.beep (beep)
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);
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// defparam freq_select_inst.MAX = 100;//100 * 34 * 20 = 68000ns
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// defparam freq_select_inst.DO = 80,
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// freq_select_inst.RE = 60,
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// freq_select_inst.MI = 50,
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// freq_select_inst.FA = 40,
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// freq_select_inst.SO = 30,
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// freq_select_inst.LA = 20,
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// freq_select_inst.XI = 10;
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endmodule |