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module pwm_beep(
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input wire sys_clk ,
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input wire sys_rst_n ,
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input wire pwm ,
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output reg beep
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);
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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beep <= 1'b1;
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end
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else if(pwm)begin
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beep <= 1'b0;
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end
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else begin
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beep <= 1'b1;
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end
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end
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endmodule
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