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23 lines
427 B
Verilog

`timescale 1ns/1ns
module music_tb();
parameter CYCLE = 20;//时钟周期
reg sys_clk ;
reg sys_rst_n ;
wire beep ;
always #(CYCLE / 2) sys_clk = ~sys_clk;
initial begin
sys_clk = 1'b0;
sys_rst_n = 1'b0;
#(CYCLE);
sys_rst_n = 1'b1;
#(CYCLE * 100 * 34);
$stop;
end
music_top music_top_inst(
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n),
.beep (beep)
);
endmodule