You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
38 lines
841 B
Verilog
38 lines
841 B
Verilog
module selector(
|
|
input wire sys_clk ,
|
|
input wire sys_rst_n ,
|
|
input wire [2: 0] key_in ,
|
|
|
|
output reg led
|
|
);
|
|
wire [2: 0] key_out;
|
|
reg flag ;
|
|
|
|
key_filter #(.KEY_W(3), .DELAY(1000_000)) key_filter_inst(//20
|
|
.sys_clk (sys_clk),
|
|
.sys_rst_n (sys_rst_n),
|
|
.key_in (key_in),
|
|
|
|
.key_out (key_out)
|
|
);
|
|
|
|
always @(posedge sys_clk or negedge sys_rst_n)begin
|
|
if(!sys_rst_n)begin
|
|
flag <= 1'b0;
|
|
end
|
|
else if(key_out[0])begin
|
|
flag <= ~flag;
|
|
end
|
|
else begin
|
|
flag <= flag;
|
|
end
|
|
end
|
|
|
|
always @(*)begin
|
|
case(flag)//按键选择0
|
|
1'b0 : led = ~key_in[1]; //选择输出按键1
|
|
1'b1 : led = ~key_in[2]; //选择按键输出2
|
|
default : led = 1'b0;
|
|
endcase
|
|
end
|
|
endmodule |