static_led/rtl/static_led.v

module static_led(
    input   wire        sys_clk     ,
    input   wire        sys_rst_n   ,

    output  reg [7: 0]  seg_led     ,//数码管段选信号
    output  reg [5: 0]  sel_led      //数码管位选信号
);
parameter MAX = 28'd50_000_000;//1s
parameter NUM = 4'd10;//数10次
reg [27: 0] cnt_s;
reg [3: 0]  cnt_10;
//cnt_s计数器设计
always @(posedge sys_clk or negedge sys_rst_n) begin
    if(!sys_rst_n)begin
        cnt_s <= 28'd0;
    end 
    else if(cnt_s == MAX - 1'd1)begin
        cnt_s <= 28'd0;
    end 
    else begin
        cnt_s <= cnt_s + 1'd1;
    end 
end
//cnt_10计数器设计
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        cnt_10 <= 4'd0;
    end 
    //记到9并且1s结束
    else if((cnt_10 == NUM - 1'd1) && (cnt_s == MAX - 1'd1))begin
        cnt_10 <= 4'd0;
    end 
    //每计1s加1
    else if(cnt_s == MAX - 1'd1)begin
        cnt_10 <= cnt_10 + 1'd1;
    end 
    //其他时钟上升沿的时候保持
    else begin
        cnt_10 <= cnt_10;
    end 
end 
//对sel_led信号进行约束
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        sel_led <= 6'b111_111;//关闭6个数码管
    end 
    else begin
        sel_led <= 6'b000_000;//开启6个数码管
    end 
end 
//对seg_led信号进行约束
always @(*)begin
    case(cnt_10)
        4'd0    :   seg_led = 8'b1100_0000;
        4'd1    :   seg_led = 8'b1111_1001;  
        4'd2    :   seg_led = 8'b1010_0100; 
        4'd3    :   seg_led = 8'b1011_0000; 
        4'd4    :   seg_led = 8'b1001_1001;             
        4'd5    :   seg_led = 8'b1001_0010;         
        4'd6    :   seg_led = 8'b1000_0010;         
        4'd7    :   seg_led = 8'b1111_1000;         
        4'd8    :   seg_led = 8'b1000_0000;  
        4'd9    :   seg_led = 8'b1001_0000; 
        default :   seg_led = 8'b1100_0000;
    endcase
end 
endmodule