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67 lines
1.9 KiB
Verilog
67 lines
1.9 KiB
Verilog
module static_led(
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input wire sys_clk ,
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input wire sys_rst_n ,
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output reg [7: 0] seg_led ,//数码管段选信号
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output reg [5: 0] sel_led //数码管位选信号
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);
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parameter MAX = 28'd50_000_000;//1s
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parameter NUM = 4'd10;//数10次
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reg [27: 0] cnt_s;
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reg [3: 0] cnt_10;
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//cnt_s计数器设计
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always @(posedge sys_clk or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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cnt_s <= 28'd0;
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end
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else if(cnt_s == MAX - 1'd1)begin
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cnt_s <= 28'd0;
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end
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else begin
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cnt_s <= cnt_s + 1'd1;
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end
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end
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//cnt_10计数器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_10 <= 4'd0;
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end
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//记到9并且1s结束
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else if((cnt_10 == NUM - 1'd1) && (cnt_s == MAX - 1'd1))begin
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cnt_10 <= 4'd0;
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end
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//每计1s加1
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else if(cnt_s == MAX - 1'd1)begin
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cnt_10 <= cnt_10 + 1'd1;
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end
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//其他时钟上升沿的时候保持
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else begin
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cnt_10 <= cnt_10;
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end
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end
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//对sel_led信号进行约束
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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sel_led <= 6'b111_111;//关闭6个数码管
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end
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else begin
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sel_led <= 6'b000_000;//开启6个数码管
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end
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end
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//对seg_led信号进行约束
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always @(*)begin
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case(cnt_10)
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4'd0 : seg_led = 8'b1100_0000;
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4'd1 : seg_led = 8'b1111_1001;
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4'd2 : seg_led = 8'b1010_0100;
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4'd3 : seg_led = 8'b1011_0000;
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4'd4 : seg_led = 8'b1001_1001;
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4'd5 : seg_led = 8'b1001_0010;
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4'd6 : seg_led = 8'b1000_0010;
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4'd7 : seg_led = 8'b1111_1000;
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4'd8 : seg_led = 8'b1000_0000;
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4'd9 : seg_led = 8'b1001_0000;
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default : seg_led = 8'b1100_0000;
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endcase
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end
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endmodule
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