uart_tiktok/hardware/rtl/uart_tx.v

`include "param.v"
module uart_tx(
    input   wire            sys_clk     ,
    input   wire            sys_rst_n   ,
    input   wire  [7: 0]    tx_din      ,//并行输入，接受模块传入
    input   wire            rx_vld      ,//接受模块，串转并有效信号


    output  wire            tx_vld      ,
    output  reg             tx_dout     //串行输出
);
parameter BAUD = `SYS_FRQ / `MAX;//波特率最大数
reg [8: 0] data_reg;//寄存数据，包含起始位
reg        tx_flag ;//发送数据有效信号
//波特率计数寄存器
reg [12: 0] cnt_bps;
wire        add_cnt_bps;
wire        end_cnt_bps;

//比特计数寄存器
reg [3: 0] cnt_bit;
wire       add_cnt_bit;
wire       end_cnt_bit;

//寄存数据
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        data_reg <= 9'hx;
    end 
    else if(rx_vld)begin
        data_reg <= {tx_din, 1'b0};//封装成数据帧
    end
    else begin
        data_reg <= data_reg;
    end 
end 
//tx_flag信号约束
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        tx_flag <= 1'b0;
    end 
    else if(rx_vld)begin
        tx_flag <= 1'b1;
    end 
    else if(end_cnt_bit)begin
        tx_flag <= 1'b0;
    end 
    else begin
        tx_flag <= tx_flag;
    end 
end 
//cnt_bps计数器设计
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        cnt_bps <= 13'd0;
    end 
    else if(add_cnt_bps)begin
        if(end_cnt_bps)begin
            cnt_bps <= 13'd0;
        end 
        else begin
            cnt_bps <= cnt_bps + 1'd1;
        end 
    end 
    else begin
        cnt_bps <= cnt_bps;
    end 
end 
assign add_cnt_bps = tx_flag;
assign end_cnt_bps = add_cnt_bps && cnt_bps == BAUD - 1'd1;
//cnt_bit计数器设计
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        cnt_bit <= 4'd0;
    end 
    else if(add_cnt_bit)begin
        if(end_cnt_bit)begin
            cnt_bit <= 4'd0;
        end 
        else begin
            cnt_bit <= cnt_bit + 1'd1;
        end 
    end 
    else begin
        cnt_bit <= cnt_bit;
    end     
end 
assign add_cnt_bit = end_cnt_bps;//波特计数器结束开启
assign end_cnt_bit = add_cnt_bit && cnt_bit == 4'd8;

//tx_dout信号进行约束
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        tx_dout <= 1'b1;
    end 
    else if(tx_flag)begin
        tx_dout <= data_reg[cnt_bit];//发送数据，并转串
    end 
    else begin
        tx_dout <= 1'b1;
    end 
end 
assign tx_vld = end_cnt_bit;
endmodule