software update

hardware/rtl/key_filter.v

@@ -0,0 +1,131 @@
+//状态机消抖模块
+module key_filter #(parameter KEY_W = 4,DELAY = 1000_000)(//20ms
+    input                       sys_clk        ,
+    input                       sys_rst_n      ,
+    input       [KEY_W-1:0]     key_in        ,
+    output  reg [KEY_W-1:0]     key_out   
+);	
+    //状态机参数定义
+    localparam  IDLE        = 4'b0001,//初始状态
+                DOWN = 4'b0010,//滤除下降沿抖动
+                HOLD        = 4'b0100,//保持稳定状态
+                UP   = 4'b1000;//滤除上升沿抖动
+
+    //中间信号定义		 
+    reg		[19:0]	cnt     ;//计数20ms
+    wire		    add_cnt ;
+    wire		    end_cnt ;
+
+    reg     [3:0]   state_c ;//现态
+    reg     [3:0]   state_n ;//次态
+
+    reg     [KEY_W-1:0]     key_r0  ;//同步打拍寄存器
+    reg     [KEY_W-1:0]     key_r1  ;
+    reg     [KEY_W-1:0]     key_r2  ;
+
+    wire    [KEY_W-1:0]     nedge   ;//下降沿检测
+    wire    [KEY_W-1:0]     pedge   ;//上升沿检测
+
+    wire              idle2down;//状态机跳转条件
+    wire              down2idle;
+    wire              down2hold;
+    wire              hold2up  ;
+    wire              up2idle  ;
+
+    //状态机
+    always @(posedge sys_clk or negedge sys_rst_n)begin 
+        if(!sys_rst_n)begin
+            state_c <= IDLE;
+        end 
+        else begin 
+            state_c <= state_n;     
+        end 
+    end
+
+    always @(*)begin 
+        case (state_c)
+            IDLE       :begin
+                if(idle2down)
+                    state_n = DOWN;
+                else
+                    state_n = state_c;
+            end
+            DOWN :begin
+                if(down2idle)
+                    state_n = IDLE;
+                else if(down2hold)
+                    state_n = HOLD;
+                else
+                    state_n = state_c;
+            end
+            HOLD       :begin
+                if(hold2up)
+                    state_n = UP;
+                else
+                    state_n = state_c;
+            end
+            UP  :begin
+                if(up2idle)
+                    state_n = IDLE;
+                else
+                    state_n = state_c;
+            end
+            default:state_n = IDLE;
+        endcase 
+    end
+
+    assign idle2down = state_c == IDLE        && (nedge );//(nedge != 0)
+    assign down2idle = state_c == DOWN && (pedge );//(pedge != 0)
+    assign down2hold = state_c == DOWN && (end_cnt);// && pedge == 0;
+    assign hold2up   = state_c == HOLD        && (pedge );//(pedge != 0)
+    assign up2idle   = state_c == UP   && (end_cnt);
+
+    //计数器
+    always @(posedge sys_clk or negedge sys_rst_n)begin 
+        if(!sys_rst_n)begin
+            cnt <= 0;
+        end 
+        else if(add_cnt)begin 
+            if(end_cnt)begin 
+                cnt <= 0;
+            end
+            else begin 
+                cnt <= cnt + 1;
+            end 
+        end
+    end 
+    assign add_cnt = (state_c == DOWN) || (state_c == UP);
+    assign end_cnt = add_cnt && (cnt == DELAY-1 || down2idle);
+
+    //同步  打拍
+    always @(posedge sys_clk or negedge sys_rst_n)begin 
+        if(!sys_rst_n)begin
+            key_r0 <= {KEY_W{1'b1}};
+            key_r1 <= {KEY_W{1'b1}};
+            key_r2 <= {KEY_W{1'b1}};
+        end 
+        else begin 
+            key_r0 <= key_in;      //同步按键输入信号
+            key_r1 <= key_r0;   //打拍
+            key_r2 <= key_r1;   
+        end 
+    end
+    //r1当前状态，r2上一个状态
+    assign nedge =  ~key_r1 & key_r2;/*(~key_r1[0] & key_r2[0]) || (~key_r1[1] & key_r2[1]);*///两种写法都行
+    assign pedge =  key_r1 & ~key_r2;/*(key_r1[0] & ~key_r2[0]) || (key_r1[1] & ~key_r2[1]);*/
+
+    //key_down
+    always @(posedge sys_clk or negedge sys_rst_n)begin 
+        if(!sys_rst_n)begin
+            key_out <= 0;
+        end 
+        else if(down2hold)begin 
+            key_out <= ~key_r1; //~key_r2
+            //key_down <= down2hold?~key_r1:0;
+        end 
+        else begin 
+            key_out <= 0;    
+        end 
+    end
+
+endmodule

hardware/rtl/param.v

@@ -0,0 +1,16 @@
+`define SYS_FRQ 50_000_000
+`define BAUD_115200
+//9600、19200、38400、57600以及115200
+`ifdef BAUD_9600
+    `define MAX 9600
+`elsif BAUD_19200
+    `define MAX 19200
+`elsif BAUD_38400
+    `define MAX 38400
+`elsif BAUD_57600
+    `define MAX 57600
+`elsif BAUD_115200
+    `define MAX 115200
+`else
+    `define MAX 115200
+`endif

hardware/rtl/uart_rx.v

@@ -0,0 +1,108 @@
+`include "param.v"
+module uart_rx(
+    input   wire        sys_clk     ,
+    input   wire        sys_rst_n   ,
+    input   wire        rx_din      ,//数据串行输入
+    input   wire        rcv_start   ,
+
+    output  wire [7: 0] rx_dout     ,//数据并行输出
+    output  wire        rx_vld      //输出信号有效
+);
+parameter BAUD = `SYS_FRQ / `MAX;//获取1bit时钟振动的次数
+reg din_reg0;//同步外来信号，和本时钟域同步
+reg din_reg1;//打拍，获取下降沿
+wire nedge;//下降沿标志
+
+reg rx_flag;//开始接受标志
+
+//对bit进行计数寄存器
+reg [3: 0] cnt_bit    ;
+wire       add_cnt_bit;
+wire       end_cnt_bit;
+//对波特率进行计数寄存器
+reg [12: 0] cnt_bps     ;
+wire        add_cnt_bps ;
+wire        end_cnt_bps ; 
+
+//数据寄存器
+reg [7: 0]  data_reg;
+always @(posedge sys_clk or negedge sys_rst_n) begin
+    if(!sys_rst_n)begin
+        din_reg0 <= 1'b1;
+        din_reg1 <= 1'b1;
+    end
+    else begin
+        din_reg0 <= rx_din;
+        din_reg1 <= din_reg0;
+    end 
+end
+assign nedge = ~din_reg0 && din_reg1;//下降沿
+
+//rx_flag信号约束
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        rx_flag <= 1'b0;
+    end 
+    else if(nedge && rcv_start)begin//检测到下降沿
+        rx_flag <= 1'b1;
+    end 
+    else if(end_cnt_bit)begin//传输完成标志
+        rx_flag <= 1'b0;
+    end
+    else begin
+        rx_flag <= rx_flag;//其他时刻保持
+    end  
+end 
+//cnt_bps计数器设计
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        cnt_bps <= 13'd0;
+    end 
+    else if(add_cnt_bps)begin
+        if(end_cnt_bps)begin
+            cnt_bps <= 13'd0;
+        end 
+        else begin
+            cnt_bps <= cnt_bps + 1'd1;
+        end 
+    end 
+    else begin
+        cnt_bps <= cnt_bps;
+    end 
+end 
+assign add_cnt_bps = rx_flag;
+assign end_cnt_bps = add_cnt_bps && cnt_bps == BAUD - 1'd1;
+//cnt_bit计数器设计
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        cnt_bit <= 4'd0;
+    end 
+    else if(add_cnt_bit)begin
+        if(end_cnt_bit)begin
+            cnt_bit <= 4'd0;
+        end 
+        else begin
+            cnt_bit <= cnt_bit + 1'd1;
+        end 
+    end 
+    else begin
+        cnt_bit <= cnt_bit;
+    end 
+end 
+assign add_cnt_bit = end_cnt_bps;//比特计数开始条件
+assign end_cnt_bit = add_cnt_bit && cnt_bit == 4'd8;//0-8
+//对data_reg进行约束
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        data_reg <= 8'hx;
+    end 
+    else if((cnt_bit >= 4'd1 && cnt_bit <= 4'd8) && (cnt_bps == BAUD >> 1))begin
+        data_reg[cnt_bit - 1'd1] = din_reg0;//对输入数据进行采样
+    end 
+    else begin
+        data_reg <= data_reg;
+    end
+end 
+assign rx_dout = data_reg;//数据输出
+assign rx_vld = end_cnt_bit;//串转并结束标志
+endmodule 

hardware/rtl/uart_top.v

@@ -0,0 +1,45 @@
+module uart_top(
+    input   wire         sys_clk    ,
+    input   wire         sys_rst_n  ,
+    input   wire         rx         ,
+    input   wire  [3: 0] key_in     ,
+    
+    output  wire         tx          
+);
+wire [7: 0] data_byte   ;
+wire [7: 0] data_out    ;
+wire [3: 0] key_out     ;
+wire        tx_vld      ;
+wire        rx_vld      ;
+reg         rcv_start   ;
+
+// uart_rx     uart_rx_inst(
+// .sys_clk        (sys_clk)   ,
+// .sys_rst_n      (sys_rst_n) ,
+// .rx_din         (rx)        ,//数据串行输入
+// .rcv_start      (rcv_start) ,   
+
+// .rx_dout        (data_byte) ,//数据并行输出
+// .rx_vld         (rx_vld)    //输出信号有效
+// );
+
+key_filter key_filter_inst(//20ms
+.sys_clk        (sys_clk),
+.sys_rst_n      (sys_rst_n),
+.key_in         (key_in),
+.key_out        (key_out)
+);	
+
+assign rx_vld = |key_out;//0001 0010 0100 1000
+assign data_out = {4'b0000, key_out};//一字节,0x01=0000_0010
+uart_tx     uart_tx_inst(
+.sys_clk        (sys_clk)   ,
+.sys_rst_n      (sys_rst_n) ,
+.tx_din         (data_out)  ,//并行输入，接受模块传入
+.rx_vld         (rx_vld)    ,//接受模块，串转并有效信
+.tx_vld         (tx_vld)    ,  
+
+.tx_dout        (tx)//串行输出
+);
+
+endmodule

hardware/rtl/uart_top.v.bak

@@ -0,0 +1,46 @@
+module uart_top(
+    input   wire         sys_clk    ,
+    input   wire         sys_rst_n  ,
+    input   wire         rx         ,
+    input   wire  [3: 0] key_in     ,
+    
+    output  wire         tx         ,
+    output  wire         led_ready    
+);
+wire [7: 0] data_byte   ;
+wire [7: 0] data_out    ;
+wire [3: 0] key_out     ;
+wire        tx_vld      ;
+wire        rx_vld      ;
+reg         rcv_start   ;
+
+// uart_rx     uart_rx_inst(
+// .sys_clk        (sys_clk)   ,
+// .sys_rst_n      (sys_rst_n) ,
+// .rx_din         (rx)        ,//数据串行输入
+// .rcv_start      (rcv_start) ,   
+
+// .rx_dout        (data_byte) ,//数据并行输出
+// .rx_vld         (rx_vld)    //输出信号有效
+// );
+
+key_filter key_filter_inst(//20ms
+.sys_clk        (sys_clk),
+.sys_rst_n      (sys_rst_n),
+.key_in         (key_in),
+.key_out        (key_out)
+);	
+
+assign rx_vld = |key_out;
+assign data_out = {4'b0000, key_out};
+uart_tx     uart_tx_inst(
+.sys_clk        (sys_clk)   ,
+.sys_rst_n      (sys_rst_n) ,
+.tx_din         (data_out)  ,//并行输入，接受模块传入
+.rx_vld         (rx_vld)    ,//接受模块，串转并有效信
+.tx_vld         (tx_vld)    ,  
+
+.tx_dout        (tx)//串行输出
+);
+
+endmodule

hardware/rtl/uart_tx.v

@@ -0,0 +1,104 @@
+`include "param.v"
+module uart_tx(
+    input   wire            sys_clk     ,
+    input   wire            sys_rst_n   ,
+    input   wire  [7: 0]    tx_din      ,//并行输入，接受模块传入
+    input   wire            rx_vld      ,//接受模块，串转并有效信号
+
+
+    output  wire            tx_vld      ,
+    output  reg             tx_dout     //串行输出
+);
+parameter BAUD = `SYS_FRQ / `MAX;//波特率最大数
+reg [8: 0] data_reg;//寄存数据，包含起始位
+reg        tx_flag ;//发送数据有效信号
+//波特率计数寄存器
+reg [12: 0] cnt_bps;
+wire        add_cnt_bps;
+wire        end_cnt_bps;
+
+//比特计数寄存器
+reg [3: 0] cnt_bit;
+wire       add_cnt_bit;
+wire       end_cnt_bit;
+
+//寄存数据
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        data_reg <= 9'hx;
+    end 
+    else if(rx_vld)begin
+        data_reg <= {tx_din, 1'b0};//封装成数据帧
+    end
+    else begin
+        data_reg <= data_reg;
+    end 
+end 
+//tx_flag信号约束
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        tx_flag <= 1'b0;
+    end 
+    else if(rx_vld)begin
+        tx_flag <= 1'b1;
+    end 
+    else if(end_cnt_bit)begin
+        tx_flag <= 1'b0;
+    end 
+    else begin
+        tx_flag <= tx_flag;
+    end 
+end 
+//cnt_bps计数器设计
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        cnt_bps <= 13'd0;
+    end 
+    else if(add_cnt_bps)begin
+        if(end_cnt_bps)begin
+            cnt_bps <= 13'd0;
+        end 
+        else begin
+            cnt_bps <= cnt_bps + 1'd1;
+        end 
+    end 
+    else begin
+        cnt_bps <= cnt_bps;
+    end 
+end 
+assign add_cnt_bps = tx_flag;
+assign end_cnt_bps = add_cnt_bps && cnt_bps == BAUD - 1'd1;
+//cnt_bit计数器设计
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        cnt_bit <= 4'd0;
+    end 
+    else if(add_cnt_bit)begin
+        if(end_cnt_bit)begin
+            cnt_bit <= 4'd0;
+        end 
+        else begin
+            cnt_bit <= cnt_bit + 1'd1;
+        end 
+    end 
+    else begin
+        cnt_bit <= cnt_bit;
+    end     
+end 
+assign add_cnt_bit = end_cnt_bps;//波特计数器结束开启
+assign end_cnt_bit = add_cnt_bit && cnt_bit == 4'd8;
+
+//tx_dout信号进行约束
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        tx_dout <= 1'b1;
+    end 
+    else if(tx_flag)begin
+        tx_dout <= data_reg[cnt_bit];//发送数据，并转串
+    end 
+    else begin
+        tx_dout <= 1'b1;
+    end 
+end 
+assign tx_vld = end_cnt_bit;
+endmodule

hardware/tcl/uart_tiktok.tcl

@@ -0,0 +1,27 @@
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+
+# Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
+# File: C:\Users\Stark-lin\Desktop\uart_tiktok\hardware\tcl\uart_tiktok.tcl
+# Generated on: Fri May 17 17:40:01 2024
+
+package require ::quartus::project
+
+set_location_assignment PIN_E1 -to sys_clk
+set_location_assignment PIN_E15 -to sys_rst_n
+set_location_assignment PIN_E16 -to key_in[0]
+set_location_assignment PIN_M15 -to key_in[1]
+set_location_assignment PIN_M16 -to key_in[2]
+set_location_assignment PIN_F8 -to key_in[3]
+set_location_assignment PIN_G1 -to tx

readme.md

@@ -0,0 +1,3 @@
+# 串口抖音
+## 1.按键数据通过串口发送给上位机控制抖音
+## 2.软件升级，可以检测任意端口号

software/go.mod

@@ -0,0 +1,33 @@
+module software
+
+go 1.22.3
+
+require (
+	github.com/StackExchange/wmi v1.2.1
+	github.com/go-vgo/robotgo v0.110.1
+	github.com/tarm/serial v0.0.0-20180830185346-98f6abe2eb07
+)
+
+require (
+	github.com/gen2brain/shm v0.0.0-20230802011745-f2460f5984f7 // indirect
+	github.com/go-ole/go-ole v1.3.0 // indirect
+	github.com/jezek/xgb v1.1.0 // indirect
+	github.com/kbinani/screenshot v0.0.0-20230812210009-b87d31814237 // indirect
+	github.com/lufia/plan9stats v0.0.0-20230326075908-cb1d2100619a // indirect
+	github.com/lxn/win v0.0.0-20210218163916-a377121e959e // indirect
+	github.com/otiai10/gosseract v2.2.1+incompatible // indirect
+	github.com/power-devops/perfstat v0.0.0-20221212215047-62379fc7944b // indirect
+	github.com/robotn/xgb v0.0.0-20190912153532-2cb92d044934 // indirect
+	github.com/robotn/xgbutil v0.0.0-20190912154524-c861d6f87770 // indirect
+	github.com/shirou/gopsutil/v3 v3.23.8 // indirect
+	github.com/shoenig/go-m1cpu v0.1.6 // indirect
+	github.com/tklauser/go-sysconf v0.3.12 // indirect
+	github.com/tklauser/numcpus v0.6.1 // indirect
+	github.com/vcaesar/gops v0.30.2 // indirect
+	github.com/vcaesar/imgo v0.40.0 // indirect
+	github.com/vcaesar/keycode v0.10.1 // indirect
+	github.com/vcaesar/tt v0.20.0 // indirect
+	github.com/yusufpapurcu/wmi v1.2.3 // indirect
+	golang.org/x/image v0.12.0 // indirect
+	golang.org/x/sys v0.12.0 // indirect
+)

software/go.sum

@@ -0,0 +1,116 @@
+github.com/BurntSushi/freetype-go v0.0.0-20160129220410-b763ddbfe298/go.mod h1:D+QujdIlUNfa0igpNMk6UIvlb6C252URs4yupRUV4lQ=
+github.com/BurntSushi/graphics-go v0.0.0-20160129215708-b43f31a4a966/go.mod h1:Mid70uvE93zn9wgF92A/r5ixgnvX8Lh68fxp9KQBaI0=
+github.com/StackExchange/wmi v1.2.1 h1:VIkavFPXSjcnS+O8yTq7NI32k0R5Aj+v39y29VYDOSA=
+github.com/StackExchange/wmi v1.2.1/go.mod h1:rcmrprowKIVzvc+NUiLncP2uuArMWLCbu9SBzvHz7e8=
+github.com/davecgh/go-spew v1.1.0/go.mod h1:J7Y8YcW2NihsgmVo/mv3lAwl/skON4iLHjSsI+c5H38=
+github.com/davecgh/go-spew v1.1.1 h1:vj9j/u1bqnvCEfJOwUhtlOARqs3+rkHYY13jYWTU97c=
+github.com/davecgh/go-spew v1.1.1/go.mod h1:J7Y8YcW2NihsgmVo/mv3lAwl/skON4iLHjSsI+c5H38=
+github.com/gen2brain/shm v0.0.0-20230802011745-f2460f5984f7 h1:VLEKvjGJYAMCXw0/32r9io61tEXnMWDRxMk+peyRVFc=
+github.com/gen2brain/shm v0.0.0-20230802011745-f2460f5984f7/go.mod h1:uF6rMu/1nvu+5DpiRLwusA6xB8zlkNoGzKn8lmYONUo=
+github.com/go-ole/go-ole v1.2.5/go.mod h1:pprOEPIfldk/42T2oK7lQ4v4JSDwmV0As9GaiUsvbm0=
+github.com/go-ole/go-ole v1.2.6/go.mod h1:pprOEPIfldk/42T2oK7lQ4v4JSDwmV0As9GaiUsvbm0=
+github.com/go-ole/go-ole v1.3.0 h1:Dt6ye7+vXGIKZ7Xtk4s6/xVdGDQynvom7xCFEdWr6uE=
+github.com/go-ole/go-ole v1.3.0/go.mod h1:5LS6F96DhAwUc7C+1HLexzMXY1xGRSryjyPPKW6zv78=
+github.com/go-vgo/robotgo v0.110.1 h1:2etpOzsBBt9KJOxDBFBVYzE4/U7gRrsnB9dxuujRMTw=
+github.com/go-vgo/robotgo v0.110.1/go.mod h1:DdJUdi6mEU8ttHMbow6hKD1TjgsfgJC/H+4dusok8Uw=
+github.com/google/go-cmp v0.5.6/go.mod h1:v8dTdLbMG2kIc/vJvl+f65V22dbkXbowE6jgT/gNBxE=
+github.com/google/go-cmp v0.5.9 h1:O2Tfq5qg4qc4AmwVlvv0oLiVAGB7enBSJ2x2DqQFi38=
+github.com/google/go-cmp v0.5.9/go.mod h1:17dUlkBOakJ0+DkrSSNjCkIjxS6bF9zb3elmeNGIjoY=
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software/main.go

@@ -0,0 +1,79 @@
+package main
+
+import (
+	"fmt"
+	"log"
+	"regexp"
+	"time"
+
+	"github.com/StackExchange/wmi"
+	"github.com/go-vgo/robotgo"
+	"github.com/tarm/serial"
+)
+
+type Win32_PnPEntity struct {
+	Name string
+}
+
+func check() string {
+	var devices []Win32_PnPEntity
+	query := `SELECT Name FROM Win32_PnPEntity WHERE Name LIKE '%(COM%'`
+
+	err := wmi.Query(query, &devices)
+	if err != nil {
+		panic(fmt.Sprintf("Failed to query WMI: %v", err))
+	}
+	re := regexp.MustCompile(`COM\d+`)
+	dev := re.FindString(devices[0].Name)
+	return dev //获取串口名字
+}
+func main() {
+	// 串口配置
+	com := check() //获取串口名字com3
+	config := &serial.Config{
+		Name: com,    // 替换为实际的串口设备路径（例如，在Windows上可能是"COM1"）
+		Baud: 115200, // 波特率，根据实际需求设置
+	}
+
+	// 打开串口
+	port, err := serial.OpenPort(config)
+	if err != nil {
+		log.Fatal(err)
+	}
+	defer port.Close()
+
+	buffer := make([]byte, 128) // 缓冲区大小根据你的数据包大小调整
+
+	for {
+		//如果有数据就读，没有就阻塞
+		n, err := port.Read(buffer) //n多少Byte
+		if err != nil {
+			log.Printf("读取错误: %v\n", err)
+			continue
+		}
+
+		if n > 0 {
+
+			// 这里可以添加处理数据的逻辑
+			if buffer[0] == 0x01 {
+				robotgo.KeyPress("up")
+			} else if buffer[0] == 0x02 {
+				robotgo.KeyPress("down")
+
+			} else if buffer[0] == 0x04 {
+				robotgo.KeyPress("f")
+
+			} else if buffer[0] == 0x08 {
+				robotgo.KeyPress("z")
+			} else {
+				log.Printf("读取到 %d 字节数据: %d\n", n, buffer[:n])
+			}
+		} else {
+			// 当没有读取到数据时，可以根据需要处理或简单跳过
+			log.Println("没有新数据")
+		}
+
+		// 可以根据需要添加适当的延迟，避免无数据时CPU占用过高
+		time.Sleep(10 * time.Millisecond)
+	}
+}

software/winres/winres.json

@@ -0,0 +1,60 @@
+{
+  "RT_GROUP_ICON": {
+    "APP": {
+      "0000": [
+        "home-logo.png"
+      ]
+    }
+  },
+  "RT_MANIFEST": {
+    "#1": {
+      "0409": {
+        "identity": {
+          "name": "",
+          "version": ""
+        },
+        "description": "",
+        "minimum-os": "win7",
+        "execution-level": "as invoker",
+        "ui-access": false,
+        "auto-elevate": false,
+        "dpi-awareness": "system",
+        "disable-theming": false,
+        "disable-window-filtering": false,
+        "high-resolution-scrolling-aware": false,
+        "ultra-high-resolution-scrolling-aware": false,
+        "long-path-aware": false,
+        "printer-driver-isolation": false,
+        "gdi-scaling": false,
+        "segment-heap": false,
+        "use-common-controls-v6": false
+      }
+    }
+  },
+  "RT_VERSION": {
+    "#1": {
+      "0000": {
+        "fixed": {
+          "file_version": "0.0.0.0",
+          "product_version": "0.0.0.0"
+        },
+        "info": {
+          "0409": {
+            "Comments": "",
+            "CompanyName": "",
+            "FileDescription": "",
+            "FileVersion": "",
+            "InternalName": "",
+            "LegalCopyright": "",
+            "LegalTrademarks": "",
+            "OriginalFilename": "",
+            "PrivateBuild": "",
+            "ProductName": "",
+            "ProductVersion": "",
+            "SpecialBuild": ""
+          }
+        }
+      }
+    }
+  }
+}