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45 lines
1.2 KiB
Verilog
45 lines
1.2 KiB
Verilog
module uart_top(
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input wire sys_clk ,
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input wire sys_rst_n ,
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input wire rx ,
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input wire [3: 0] key_in ,
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output wire tx
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);
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wire [7: 0] data_byte ;
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wire [7: 0] data_out ;
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wire [3: 0] key_out ;
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wire tx_vld ;
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wire rx_vld ;
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reg rcv_start ;
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// uart_rx uart_rx_inst(
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// .sys_clk (sys_clk) ,
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// .sys_rst_n (sys_rst_n) ,
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// .rx_din (rx) ,//数据串行输入
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// .rcv_start (rcv_start) ,
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// .rx_dout (data_byte) ,//数据并行输出
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// .rx_vld (rx_vld) //输出信号有效
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// );
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key_filter key_filter_inst(//20ms
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.sys_clk (sys_clk),
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.sys_rst_n (sys_rst_n),
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.key_in (key_in),
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.key_out (key_out)
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);
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assign rx_vld = |key_out;//0001 0010 0100 1000
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assign data_out = {4'b0000, key_out};//一字节,0x01=0000_0010
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uart_tx uart_tx_inst(
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.sys_clk (sys_clk) ,
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.sys_rst_n (sys_rst_n) ,
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.tx_din (data_out) ,//并行输入，接受模块传入
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.rx_vld (rx_vld) ,//接受模块，串转并有效信
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.tx_vld (tx_vld) ,
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.tx_dout (tx)//串行输出
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);
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endmodule |