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module uart_top (
input wire sys_clk ,
input wire sys_rst_n ,
input wire rx ,
input wire [ 3 : 0 ] key_in ,
output wire tx ,
output wire led_ready
) ;
wire [ 7 : 0 ] data_byte ;
wire [ 7 : 0 ] data_out ;
wire [ 3 : 0 ] key_out ;
wire tx_vld ;
wire rx_vld ;
reg rcv_start ;
// uart_rx uart_rx_inst (
// . sys_clk ( sys_clk ) ,
// . sys_rst_n ( sys_rst_n ) ,
// . rx_din ( rx ) , // 数 据 串 行 输 入
// . rcv_start ( rcv_start ) ,
// . rx_dout ( data_byte ) , // 数 据 并 行 输 出
// . rx_vld ( rx_vld ) // 输 出 信 号 有 效
// ) ;
key_filter key_filter_inst ( // 20 ms
. sys_clk ( sys_clk ) ,
. sys_rst_n ( sys_rst_n ) ,
. key_in ( key_in ) ,
. key_out ( key_out )
) ;
assign rx_vld = | key_out ;
assign data_out = { 4 ' b0000 , key_out } ;
uart_tx uart_tx_inst (
. sys_clk ( sys_clk ) ,
. sys_rst_n ( sys_rst_n ) ,
. tx_din ( data_out ) , // 并 行 输 入 ， 接 受 模 块 传 入
. rx_vld ( rx_vld ) , // 接 受 模 块 ， 串 转 并 有 效 信
. tx_vld ( tx_vld ) ,
. tx_dout ( tx ) // 串 行 输 出
) ;
endmodule