module gen_clk(
    input  wire  sys_clk    ,
    input  wire  sys_rst_n  ,

    output wire  clk_25     ,
    output wire  vga_rst_n
);
wire locked;
assign vga_rst_n = sys_rst_n & locked;
pll	pll_inst (
	.areset ( ~sys_rst_n )  ,
	.inclk0 ( sys_clk )     ,
	.c0     ( clk_25 )      ,
	.locked ( locked )
	);
endmodule