module top(
    input  wire         sys_clk     ,
    input  wire         sys_rst_n   ,

    output wire [15: 0] vga_data    ,
    output wire         hsync       ,
    output wire         vsync

);
wire                clk_25      ;
wire                vga_rst_n   ;
wire    [9: 0]      pixel_x     ;
wire    [9: 0]      pixel_y     ;
wire    [15: 0]     rgb_data    ;
vga_ctrl    vga_ctrl_inst(
.clk_25      (clk_25),
.vga_rst_n   (vga_rst_n),
.rgb_data    (rgb_data),

.hsync       (hsync),
.vsync       (vsync),
.pixel_x     (pixel_x),
.pixel_y     (pixel_y),
.vga_data    (vga_data)
);

gen_clk gen_clk_inst(
.sys_clk    (sys_clk),
.sys_rst_n  (sys_rst_n),

.clk_25     (clk_25),
.vga_rst_n  (vga_rst_n)
);

data_gen    data_gen_inst(
.clk_25     (clk_25),
.vga_rst_n  (vga_rst_n),
.pixel_x    (pixel_x),
.pixel_y    (pixel_y),

.rgb_data   (rgb_data)
);
endmodule