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43 lines
869 B
Verilog
43 lines
869 B
Verilog
module top(
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input wire sys_clk ,
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input wire sys_rst_n ,
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output wire [15: 0] vga_data ,
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output wire hsync ,
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output wire vsync
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);
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wire clk_25 ;
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wire vga_rst_n ;
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wire [9: 0] pixel_x ;
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wire [9: 0] pixel_y ;
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wire [15: 0] rgb_data ;
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vga_ctrl vga_ctrl_inst(
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.clk_25 (clk_25),
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.vga_rst_n (vga_rst_n),
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.rgb_data (rgb_data),
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.hsync (hsync),
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.vsync (vsync),
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.pixel_x (pixel_x),
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.pixel_y (pixel_y),
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.vga_data (vga_data)
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);
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gen_clk gen_clk_inst(
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.sys_clk (sys_clk),
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.sys_rst_n (sys_rst_n),
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.clk_25 (clk_25),
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.vga_rst_n (vga_rst_n)
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);
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data_gen data_gen_inst(
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.clk_25 (clk_25),
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.vga_rst_n (vga_rst_n),
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.pixel_x (pixel_x),
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.pixel_y (pixel_y),
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.rgb_data (rgb_data)
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);
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endmodule
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