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89 lines
2.8 KiB
Verilog
89 lines
2.8 KiB
Verilog
module vga_ctrl(
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input wire clk_25 ,
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input wire vga_rst_n ,
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input wire [15: 0] rgb_data ,
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output wire hsync ,
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output wire vsync ,
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output wire [9: 0] pixel_x ,
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output wire [9: 0] pixel_y ,
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output wire [15: 0] vga_data
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);
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//行
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parameter H_SYNC = 10'd96 ,
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H_BACK = 10'd40 ,
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H_LEFT = 10'd8 ,
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H_AREA = 10'd640 ,
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H_RIGHT = 10'd8 ,
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H_FRONT = 10'd8 ,
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H_TOTAL = 10'd800 ;
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//列
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parameter V_SYNC = 10'd2 ,
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V_BACK = 10'd25 ,
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V_TOP = 10'd8 ,
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V_AREA = 10'd480,
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V_BUTTON = 10'd8 ,
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V_FRONT = 10'd2 ,
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V_TOTAL = 10'd525;
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//像素计数
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reg [9: 0] cnt_pixel;
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wire add_cnt_pixel;
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wire end_cnt_pixel;
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//行计数
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reg [9: 0] cnt_row;
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wire add_cnt_row;
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wire end_cnt_row;
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wire area_vld;
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wire vld_req ;
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always @(posedge clk_25 or negedge vga_rst_n) begin
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if(!vga_rst_n)begin
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cnt_pixel <= 10'd0;
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end
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else if(add_cnt_pixel)begin
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if(end_cnt_pixel)begin
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cnt_pixel <= 10'd0;
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end
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else begin
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cnt_pixel <= cnt_pixel + 1'd1;
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end
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end
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else begin
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cnt_pixel <= cnt_pixel;
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end
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end
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assign add_cnt_pixel = 1'b1;
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assign end_cnt_pixel = add_cnt_pixel && cnt_pixel == (H_TOTAL - 1'd1);
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always @(posedge clk_25 or negedge vga_rst_n)begin
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if(!vga_rst_n)begin
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cnt_row <= 10'd0;
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end
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else if(add_cnt_row)begin
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if(end_cnt_row)begin
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cnt_row <= 10'd0;
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end
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else begin
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cnt_row <= cnt_row + 1'd1;
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end
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end
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else begin
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cnt_row <= cnt_row;
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end
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end
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assign add_cnt_row = end_cnt_pixel;
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assign end_cnt_row = add_cnt_row && cnt_row == V_TOTAL - 1'd1;
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assign hsync = (cnt_pixel <= H_SYNC - 1'd1) ? 1'b1: 1'b0;
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assign vsync = (cnt_row <= V_SYNC - 1'd1) ? 1'b1: 1'b0;
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assign area_vld = (cnt_pixel >= (H_SYNC + H_BACK + H_LEFT)) &&
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(cnt_pixel < (H_SYNC + H_BACK + H_LEFT + H_AREA)) &&
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(cnt_row >= (V_SYNC + V_BACK + V_TOP)) &&
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(cnt_row < (V_SYNC + V_BACK + V_TOP + V_AREA));
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assign vld_req = (cnt_pixel >= (H_SYNC + H_BACK + H_LEFT - 1'd1)) &&
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(cnt_pixel < (H_SYNC + H_BACK + H_LEFT + H_AREA - 1'd1)) &&
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(cnt_row >= (V_SYNC + V_BACK + V_TOP)) &&
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(cnt_row < (V_SYNC + V_BACK + V_TOP + V_AREA));
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//超前一个时钟周期，目的是为了时序对齐
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assign pixel_x = (vld_req == 1'b1) ? (cnt_pixel - (H_SYNC + H_BACK + H_LEFT - 1'b1)): 10'h3ff;
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assign pixel_y = (vld_req == 1'b1) ? (cnt_row - (V_SYNC + V_BACK + V_TOP)): 10'h3ff;
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assign vga_data = (area_vld == 1'b1) ? rgb_data: 16'h0000;
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endmodule |