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57 lines
1.6 KiB
Verilog
57 lines
1.6 KiB
Verilog
module data_gen(
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input wire clk_25 ,
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input wire vga_rst_n ,
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input wire [9: 0] pixel_x ,
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input wire [9: 0] pixel_y ,
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output reg [15: 0] rgb_data
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);
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parameter RED = 16'hF800 , //红色
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ORANGE = 16'hFC00 , //橙色
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YELLOW = 16'hFFE0 , //黄色
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GREEN = 16'h07E0 , //绿色
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CYAN = 16'h07FF , //青色
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BLUE = 16'h001F , //蓝色
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PURPPLE = 16'hF81F, //紫色
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BLACK = 16'h0000 , //黑色
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WHITE = 16'hFFFF , //白色
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GRAY = 16'hD69A ;
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always @(posedge clk_25 or negedge vga_rst_n)begin
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if(!vga_rst_n)begin
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rgb_data <= 16'h0000;
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end
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else if((pixel_x >= 0) && (pixel_x < 47))begin
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rgb_data <= RED;
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end
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else if((pixel_x >=48) && (pixel_x < 95))begin
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rgb_data <= ORANGE;
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end
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else if((pixel_x >= 96) && (pixel_x < 143))begin
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rgb_data <= YELLOW;
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end
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else if((pixel_x >= 144) && (pixel_x < 192)) begin
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rgb_data <= GREEN;
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end
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else if((pixel_x >= 192) && (pixel_x < 240)) begin
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rgb_data <= CYAN;
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end
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else if((pixel_x >= 240) && (pixel_x < 288)) begin
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rgb_data <= BLUE;
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end
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else if((pixel_x >= 288) && (pixel_x < 336)) begin
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rgb_data <= PURPPLE;
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end
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else if((pixel_x >= 336) && (pixel_x < 384)) begin
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rgb_data <= BLACK;
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end
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else if((pixel_x >= 384) && (pixel_x < 432)) begin
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rgb_data <= WHITE;
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end
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else if((pixel_x >= 432) && (pixel_x < 480))begin
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rgb_data <= GRAY;
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end
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else begin
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rgb_data <= 16'h0000;
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end
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end
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endmodule |