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module gen_clk(
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input wire sys_clk ,
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input wire sys_rst_n ,
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output wire clk_25 ,
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output wire vga_rst_n
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);
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wire locked;
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assign vga_rst_n = sys_rst_n & locked;
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pll pll_inst (
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.areset ( ~sys_rst_n ) ,
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.inclk0 ( sys_clk ) ,
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.c0 ( clk_25 ) ,
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.locked ( locked )
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);
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endmodule |