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matrix led

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lincaigui 7 months ago
parent 8ea7304780
commit 695c3033e9
5 changed files with 133 additions and 7 deletions
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doc/ws2812时序图.vsdx
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74
rtl/data_cfg.v
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@ -0,0 +1,74 @@
module data_cfg(
input wire [4: 0] cnt_bit,
input wire [6: 0] cnt_led,
output wire bit
);
wire [23: 0] data[63: 0];//数据
assign bit = data[cnt_led][23 - cnt_bit];
assign data[00] = {8'hff, 8'hff, 8'hff};//GRB
assign data[01] = {8'h00, 8'h00, 8'h00};//GRB
assign data[02] = {8'h00, 8'hff, 8'h00};//GRB
assign data[03] = {8'h00, 8'h00, 8'h00};//GRB
assign data[04] = {8'h00, 8'h00, 8'h00};//GRB
assign data[05] = {8'h00, 8'h00, 8'h00};//GRB
assign data[06] = {8'h00, 8'h00, 8'h00};//GRB
assign data[07] = {8'h00, 8'h00, 8'h00};//GRB
assign data[08] = {8'h00, 8'h00, 8'h00};//GRB
assign data[09] = {8'h00, 8'h00, 8'h00};//GRB
assign data[10] = {8'h00, 8'h00, 8'h00};//GRB
assign data[11] = {8'h00, 8'h00, 8'h00};//GRB
assign data[12] = {8'h00, 8'h00, 8'h00};//GRB
assign data[13] = {8'h00, 8'h00, 8'h00};//GRB
assign data[14] = {8'h00, 8'h00, 8'h00};//GRB
assign data[15] = {8'h00, 8'h00, 8'h00};//GRB
assign data[16] = {8'h00, 8'h00, 8'h00};//GRB
assign data[17] = {8'h00, 8'h00, 8'h00};//GRB
assign data[18] = {8'h00, 8'h00, 8'h00};//GRB
assign data[19] = {8'h00, 8'h00, 8'h00};//GRB
assign data[20] = {8'h00, 8'h00, 8'h00};//GRB
assign data[21] = {8'h00, 8'h00, 8'h00};//GRB
assign data[22] = {8'h00, 8'h00, 8'h00};//GRB
assign data[23] = {8'h00, 8'h00, 8'h00};//GRB
assign data[24] = {8'h00, 8'h00, 8'h00};//GRB
assign data[25] = {8'h00, 8'h00, 8'h00};//GRB
assign data[26] = {8'h00, 8'h00, 8'h00};//GRB
assign data[27] = {8'h00, 8'h00, 8'h00};//GRB
assign data[28] = {8'h00, 8'h00, 8'h00};//GRB
assign data[29] = {8'h00, 8'h00, 8'h00};//GRB
assign data[30] = {8'h00, 8'h00, 8'h00};//GRB
assign data[31] = {8'h00, 8'h00, 8'h00};//GRB
assign data[32] = {8'h00, 8'h00, 8'h00};//GRB
assign data[33] = {8'h00, 8'h00, 8'h00};//GRB
assign data[34] = {8'h00, 8'h00, 8'h00};//GRB
assign data[35] = {8'h00, 8'h00, 8'h00};//GRB
assign data[36] = {8'h00, 8'h00, 8'h00};//GRB
assign data[37] = {8'h00, 8'h00, 8'h00};//GRB
assign data[38] = {8'h00, 8'h00, 8'h00};//GRB
assign data[39] = {8'h00, 8'h00, 8'h00};//GRB
assign data[40] = {8'h00, 8'h00, 8'h00};//GRB
assign data[41] = {8'h00, 8'h00, 8'h00};//GRB
assign data[42] = {8'h00, 8'h00, 8'h00};//GRB
assign data[43] = {8'h00, 8'h00, 8'h00};//GRB
assign data[44] = {8'h00, 8'h00, 8'h00};//GRB
assign data[45] = {8'h00, 8'h00, 8'h00};//GRB
assign data[46] = {8'h00, 8'h00, 8'h00};//GRB
assign data[47] = {8'h00, 8'h00, 8'h00};//GRB
assign data[48] = {8'h00, 8'h00, 8'h00};//GRB
assign data[49] = {8'h00, 8'h00, 8'h00};//GRB
assign data[50] = {8'h00, 8'h00, 8'h00};//GRB
assign data[51] = {8'h00, 8'h00, 8'h00};//GRB
assign data[52] = {8'h00, 8'h00, 8'h00};//GRB
assign data[53] = {8'h00, 8'h00, 8'h00};//GRB
assign data[54] = {8'h00, 8'h00, 8'h00};//GRB
assign data[55] = {8'h00, 8'h00, 8'h00};//GRB
assign data[56] = {8'h00, 8'h00, 8'h00};//GRB
assign data[57] = {8'h00, 8'h00, 8'h00};//GRB
assign data[58] = {8'h00, 8'h00, 8'h00};//GRB
assign data[59] = {8'h00, 8'h00, 8'h00};//GRB
assign data[60] = {8'h00, 8'h00, 8'h00};//GRB
assign data[61] = {8'h00, 8'h00, 8'h00};//GRB
assign data[62] = {8'h00, 8'h00, 8'h00};//GRB
assign data[63] = {8'h00, 8'h00, 8'h00};//GRB
endmodule

10
rtl/ws2812_ctrl.v
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@ -3,7 +3,9 @@ module ws2812_ctrl(
input wire sys_rst_n ,
input wire bit ,
output wire dout
output wire dout ,
output reg [4: 0] cnt_bit ,
output reg [6: 0] cnt_led
);
parameter T0H = 4'd15 ,//bit0的高电平
T0L = 6'd40 ,//bit0的低电平
@ -19,11 +21,11 @@ reg [6: 0] cnt_1;//bit1计数寄存器
wire add_cnt1;//bit1开始计数条件
wire end_cnt1;//bit1结束计数条件
reg [4: 0] cnt_bit;//24个bit计数寄存器
// reg [4: 0] cnt_bit;//24个bit计数寄存器
wire add_cnt_bit;//24bit计数器开始计数条件
wire end_cnt_bit;//24bit计数器结束计数条件
reg [6: 0] cnt_led;//64个led计数寄存器
// reg [6: 0] cnt_led;//64个led计数寄存器
wire add_cnt_led;//64个led计数器开始计数条件
wire end_cnt_led;//64个led计数器结束计数条件
@ -148,5 +150,5 @@ always @(posedge sys_clk or negedge sys_rst_n)begin
end
end
//dout输出逻辑
assign dout = (flag_rst == 0) ? ((cnt_0 < T0H ? 1'b0 : 1'b1) | (cnt_1 < T1H ? 1'b0 : 1'b1)): 1'b0;
assign dout = (flag_rst == 0) ? (((bit == 0 && cnt_0 < T0H) ? 1'b1 : 1'b0) | ((bit == 1 && cnt_1 < T1H) ? 1'b1 : 1'b0)): 1'b0;
endmodule

27
rtl/ws2812_top.v
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module ws2812_top(
input wire sys_clk ,
input wire sys_rst_n ,
output wire dout
);
wire bit ;
wire [4: 0] cnt_bit;
wire [6: 0] cnt_led;
ws2812_ctrl ws2812_ctrl_inst(
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n),
.bit (bit),
.dout (dout),
.cnt_bit (cnt_bit),
.cnt_led (cnt_led)
);
data_cfg data_cfg_inst(
.cnt_bit (cnt_bit),
.cnt_led (cnt_led),
.bit (bit)
);
endmodule

23
tcl/ws2812_led.tcl
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# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
# Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
# File: C:\Users\Stark-lin\Desktop\ws2812_led\tcl\ws2812_led.tcl
# Generated on: Mon Apr 22 10:12:26 2024
package require ::quartus::project
set_location_assignment PIN_K6 -to dout
set_location_assignment PIN_E1 -to sys_clk
set_location_assignment PIN_E15 -to sys_rst_n
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