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module ws2812_ctrl(
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input wire sys_clk ,
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input wire sys_rst_n ,
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input wire bit ,
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output wire dout ,
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output reg [4: 0] cnt_bit ,
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output reg [6: 0] cnt_led
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);
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parameter T0H = 4'd15 ,//bit0的高电平
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T0L = 6'd40 ,//bit0的低电平
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T1H = 6'd40 ,//bit1的高电平
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T1L = 6'd40 ,//bit1的低电平
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RST = 14'd15000 ;//64个led数据发完的复位信号时间，低电平0
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reg [5: 0] cnt_0;//bit0计数寄存器
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wire add_cnt0;//bit0开始计数条件
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wire end_cnt0;//bit0结束计数条件
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reg [6: 0] cnt_1;//bit1计数寄存器
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wire add_cnt1;//bit1开始计数条件
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wire end_cnt1;//bit1结束计数条件
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// reg [4: 0] cnt_bit;//24个bit计数寄存器
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wire add_cnt_bit;//24bit计数器开始计数条件
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wire end_cnt_bit;//24bit计数器结束计数条件
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// reg [6: 0] cnt_led;//64个led计数寄存器
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wire add_cnt_led;//64个led计数器开始计数条件
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wire end_cnt_led;//64个led计数器结束计数条件
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reg [13: 0] cnt_rst;//复位计数寄存器
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wire add_cnt_rst;//复位计数器开始计数条件
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wire end_cnt_rst;//复位计数器结束计数条件
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reg flag_rst;//复位信号开始寄存器
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//bit0计数器设计
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always @(posedge sys_clk or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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cnt_0 <= 6'd0;
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end
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else if(add_cnt0)begin
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if(end_cnt0)begin
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cnt_0 <= 6'd0;
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end
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else begin
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cnt_0 <= cnt_0 + 1'd1;
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end
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end
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else begin
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cnt_0 <= 6'd0;
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end
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end
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assign add_cnt0 = ~bit && flag_rst == 0;//如果bit是0，并且复位计数器没有开启，则计数器开始计数
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assign end_cnt0 = add_cnt0 && (cnt_0 == T0H + T0L-1);
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//cnt_1计数器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_1 <= 7'd0;
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end
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else if(add_cnt1)begin
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if(end_cnt1)begin
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cnt_1 <= 7'd0;
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end
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else begin
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cnt_1 <= cnt_1 + 1'd1;
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end
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end
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else begin
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cnt_1 <= 7'd0;
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end
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end
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assign add_cnt1 = bit && flag_rst == 0;//如果bit是1，并且复位计数器没有开启，则计数器开始计数
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assign end_cnt1 = add_cnt1 && (cnt_1 == T1H + T1L-1);
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//cnt_bit计数器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_bit <= 5'd0;
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end
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else if(add_cnt_bit)begin
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if(end_cnt_bit)begin
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cnt_bit <= 5'd0;
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end
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else begin
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cnt_bit <= cnt_bit + 1'd1;
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end
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end
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else begin
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cnt_bit <= cnt_bit;//其他时刻保持cnt_bit
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end
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end
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assign add_cnt_bit = end_cnt0 || end_cnt1;//bit0或者bit1结束计数条件成立
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assign end_cnt_bit = add_cnt_bit && (cnt_bit == 5'd23);//24个bit结束计数条件成立
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//cnt_led计数器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_led <= 7'd0;
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end
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else if(add_cnt_led)begin
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if(end_cnt_led)begin
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cnt_led <= 7'd0;
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end
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else begin
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cnt_led <= cnt_led + 1'd1;
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end
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end
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else begin
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cnt_led <= cnt_led;
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end
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end
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assign add_cnt_led = end_cnt_bit;
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assign end_cnt_led = add_cnt_led && (cnt_led == 7'd63);
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//cnt_rst计数器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_rst <= 14'd0;
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end
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else if(add_cnt_rst)begin
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if(end_cnt_rst)begin
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cnt_rst <= 14'd0;
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end
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else begin
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cnt_rst <= cnt_rst + 1'd1;
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end
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end
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else begin
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cnt_rst <= cnt_rst;
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end
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end
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assign add_cnt_rst = flag_rst;
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assign end_cnt_rst = add_cnt_rst && (cnt_rst == RST - 1);
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//flag_rst寄存器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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flag_rst <= 1'b0;//初始化0，复位计数器关闭
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end
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else if(end_cnt_led)begin//64个led数据发送完成，复位计数器打开
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flag_rst <= 1'b1;
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end
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else if(end_cnt_rst)begin//复位计数器结束，复位计数器关闭
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flag_rst <= 1'b0;
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end
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else begin
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flag_rst <= flag_rst;//其他时刻保持flag_rst
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end
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end
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//dout输出逻辑
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assign dout = (flag_rst == 0) ? (((bit == 0 && cnt_0 < T0H) ? 1'b1 : 1'b0) | ((bit == 1 && cnt_1 < T1H) ? 1'b1 : 1'b0)): 1'b0;
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endmodule
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